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[174.138.202.16]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-5030032c987sm119710161cf.32.2026.01.27.07.23.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Jan 2026 07:23:53 -0800 (PST) From: Raymond Mao To: opensbi@lists.infradead.org Cc: scott@riscstar.com, dave.patel@riscstar.com, raymond.mao@riscstar.com, robin.randhawa@sifive.com, samuel.holland@sifive.com, anup.patel@qti.qualcomm.com, anuppate@qti.qualcomm.com, dhaval@rivosinc.com, peter.lin@sifive.com Subject: [RFC PATCH 1/2] lib: sbi: introduce INTC abstraction for wired interrupts Date: Tue, 27 Jan 2026 10:23:41 -0500 Message-Id: <20260127152342.1231995-2-raymondmaoca@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260127152342.1231995-1-raymondmaoca@gmail.com> References: <20260127152342.1231995-1-raymondmaoca@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260127_072357_468389_961E68F5 X-CRM114-Status: GOOD ( 14.27 ) X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "opensbi" Errors-To: opensbi-bounces+opensbi=archiver.kernel.org@lists.infradead.org From: Raymond Mao Add a wired interrupt-controller (INTC) abstraction to OpenSBI. This introduces a small provider interface based on claim/complete/mask/unmak semantics, allowing to register a wired interrupt controller as a provider. Plus, add virtual IRQ number mapping to avoid exposure of hwirq. Signed-off-by: Raymond Mao --- sbi_intc.h | 99 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 99 insertions(+) create mode 100644 sbi_intc.h diff --git a/sbi_intc.h b/sbi_intc.h new file mode 100644 index 00000000..f51974c9 --- /dev/null +++ b/sbi_intc.h @@ -0,0 +1,99 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2026 RISCstar Solutions Corporation. + * + * Author: Raymond Mao + */ + +#ifndef __SBI_INTC_H__ +#define __SBI_INTC_H__ + +#include + +/* Handler for a specified IRQ number */ +typedef int (*sbi_intc_irq_handler_t)(u32 irq, void *priv); + +/* + * Provider capabilities, at the moment it contains the maximum valid source ID + * but extensible in the future + */ +struct sbi_intc_provider_caps { + /* + * Maximum supported wired source ID for this provider. + * + * For APLIC this corresponds to the highest valid source ID (1..N). + * The INTC core treats this as an abstract provider source ID space. + */ + u32 max_src; +}; + +/* Provider operations */ +struct sbi_intc_provider_ops { + /* + * Query provider capabilities. + * + * This avoids exposing provider-specific limits (such as APLIC + * num_source) through the registration API. + */ + int (*get_caps)(void *ctx, struct sbi_intc_provider_caps *caps); + + /* + * Claim a pending wired interrupt on current hart. + * Returns: + * SBI_OK : *hwirq is valid + * SBI_ENOENT : no pending wired interrupt + * <0 : error + */ + int (*claim)(void *ctx, u32 *irq); + + /* + * Complete/acknowledge a previously claimed wired interrupt + * (if required by HW). + * Some HW may not require an explicit completion. + */ + void (*complete)(void *ctx, u32 irq); + + /* + * mask/unmask a wired interrupt line. + * + * These are required for reliable couriering of level-triggered device + * interrupts to S-mode: mask in M-mode before enqueueing, and unmask + * after S-mode has cleared the device interrupt source. + */ + void (*mask)(void *ctx, u32 irq); + void (*unmask)(void *ctx, u32 irq); +}; + +/* Register the active wired interrupt provider, e.g. APLIC, via ops and ctx */ +int sbi_intc_register_provider(const struct sbi_intc_provider_ops *ops, + void *ctx); + +/* + * Optional: map a IRQ number (irq) to a hardware wired IRQ (hwirq). + * + * If no explicit mapping exists, 'irq==hwirq' is assumed. + * + * This allows upper layers (e.g. VIRQ courier/emulation) to use stable irq + * identifiers without exposing the wired controller's hwirq numbering. + */ +int sbi_intc_map_irq(u32 irq, u32 hwirq); +int sbi_intc_unmap_irq(u32 irq); +u32 sbi_intc_irq_to_hwirq(u32 irq); +u32 sbi_intc_hwirq_to_irq(u32 hwirq); + +/* Set/clear handler for a specified IRQ number */ +int sbi_intc_set_handler(u32 irq, sbi_intc_irq_handler_t handler, void *priv); +int sbi_intc_clear_handler(u32 irq); + +/* + * Platform independent mask/unmak wrappers on top of platform registered + * mask/unmask ops functions. + */ +void sbi_intc_mask_irq(u32 irq); +void sbi_intc_unmask_irq(u32 irq); + +/* External interrupt handler (for irqchip device hook 'irqchip.irq_handle') */ +int sbi_intc_handle_external_irq(void); + +#endif -- 2.25.1 -- opensbi mailing list opensbi@lists.infradead.org http://lists.infradead.org/mailman/listinfo/opensbi