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[174.138.202.16]) by smtp.gmail.com with ESMTPSA id af79cd13be357-8c71b29f796sm1136907485a.22.2026.02.02.07.02.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Feb 2026 07:02:22 -0800 (PST) From: Raymond Mao To: opensbi@lists.infradead.org Cc: scott@riscstar.com, dave.patel@riscstar.com, raymond.mao@riscstar.com, robin.randhawa@sifive.com, samuel.holland@sifive.com, anup.patel@qti.qualcomm.com, anuppate@qti.qualcomm.com, dhaval@rivosinc.com, peter.lin@sifive.com Subject: [PATCH v2 1/2] lib: sbi: introduce abstraction for wired interrupt handling Date: Mon, 2 Feb 2026 10:02:06 -0500 Message-Id: <20260202150207.1331811-2-raymondmaoca@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260202150207.1331811-1-raymondmaoca@gmail.com> References: <20260202150207.1331811-1-raymondmaoca@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260202_070226_426990_7033E809 X-CRM114-Status: UNSURE ( 9.61 ) X-CRM114-Notice: Please train this message. X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "opensbi" Errors-To: opensbi-bounces+opensbi=archiver.kernel.org@lists.infradead.org From: Raymond Mao Add wired interrupt handling abstraction into irqchip. This introduces a small provider interface based on claim/complete/mask/unmak semantics, allowing to register a wired interrupt controller as a provider. Signed-off-by: Raymond Mao --- include/sbi/sbi_irqchip.h | 52 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/include/sbi/sbi_irqchip.h b/include/sbi/sbi_irqchip.h index e0ae12f5..27b88765 100644 --- a/include/sbi/sbi_irqchip.h +++ b/include/sbi/sbi_irqchip.h @@ -27,6 +27,38 @@ struct sbi_irqchip_device { int (*irq_handle)(void); }; +/* Handler for a specified hwirq */ +typedef int (*sbi_irqchip_irq_handler_t)(void *priv); + +/* Provider operations */ +struct sbi_irqchip_provider_ops { + /* + * Claim a pending wired interrupt on current hart. + * Returns: + * SBI_OK : *hwirq is valid + * SBI_ENOENT : no pending wired interrupt + * <0 : error + */ + int (*claim)(void *ctx, u32 *hwirq); + + /* + * Complete/acknowledge a previously claimed wired interrupt + * (if required by HW). + * Some HW may not require an explicit completion. + */ + void (*complete)(void *ctx, u32 hwirq); + + /* + * mask/unmask a wired interrupt line. + * + * These are required for reliable couriering of level-triggered device + * interrupts to S-mode: mask in M-mode before enqueueing, and unmask + * after S-mode has cleared the device interrupt source. + */ + void (*mask)(void *ctx, u32 hwirq); + void (*unmask)(void *ctx, u32 hwirq); +}; + /** * Process external interrupts * @@ -46,4 +78,24 @@ int sbi_irqchip_init(struct sbi_scratch *scratch, bool cold_boot); /** Exit interrupt controllers */ void sbi_irqchip_exit(struct sbi_scratch *scratch); +/* + * Register the active wired interrupt provider. + * - max_hwirq specifies the highest valid hwirq ID. + */ +int sbi_irqchip_register_provider(const struct sbi_irqchip_provider_ops *ops, + void *ctx, u32 max_hwirq); + +u32 sbi_irqchip_get_max_src(void); + +/* Set/clear handler for a specified hwirq */ +int sbi_irqchip_set_handler(u32 hwirq, sbi_irqchip_irq_handler_t handler, + void *priv); +int sbi_irqchip_clear_handler(u32 hwirq); + +void sbi_irqchip_mask_irq(u32 hwirq); +void sbi_irqchip_unmask_irq(u32 hwirq); + +/* external interrupt handler (irqchip device hook) */ +int sbi_irqchip_handle_external_irq(void); + #endif -- 2.25.1 -- opensbi mailing list opensbi@lists.infradead.org http://lists.infradead.org/mailman/listinfo/opensbi