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Tue, 10 Feb 2026 01:42:46 -0800 (PST) Received: from m91p.airy.home ([172.92.174.155]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a9521b8d79sm133219215ad.61.2026.02.10.01.42.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Feb 2026 01:42:45 -0800 (PST) From: Bo Gan To: opensbi@lists.infradead.org, dramforever@live.com, anup.patel@oss.qualcomm.com Cc: anup@brainfault.org, cleger@rivosinc.com, samuel.holland@sifive.com Subject: [PATCH 0/7] Fixes for load/store misaligned and access faults Date: Tue, 10 Feb 2026 01:40:37 -0800 Message-Id: <20260210094044.72591-1-ganboing@gmail.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260210_014248_135704_E03B4A9B X-CRM114-Status: GOOD ( 12.38 ) X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "opensbi" Errors-To: opensbi-bounces+opensbi=archiver.kernel.org@lists.infradead.org Re-visit the load/store misaligned and access fault handlers to fix issues related to coding patterns, floating-point state, and instruction decoding: a. Vector misaligned load/store emulator is invoked improperly b. vsstatus.FS is not set dirty when V=1 c. No checking of previous XLEN, resulting in wrong insn decoding d. Load/Store base address is wrongly assumed to be trap address e. High 32-bits of tinst needs to be checked against 0 The pathset is validated on a modified QEMU[1] that exposed misaligned faults, and QEMU[2], which further disabled the insn transformation. [2] covers more insn decoding branches, including the particular ones which can trigger the wrong decoding (c) The patchset is also validated on Sifive P550 core (ESWIN EIC7700), which is RV64-only in M/(V)S/(V)U, no HW misaligned support, no vector, and mtinst always 0. Refer to [3] for the git repo/branch that has all 6 patches applied along with the test case that exercises all integer and floating-point load/store instructions. Test case used is available in PATCH 7. There's no change to the behavior of the vector misaligned load/store handler. However, I've found additional issues with them: - `uint8_t mask[VLEN_MAX / 8]` in sbi_trap_v_ldst.c is 8KB, which can overflow the default 4KB stack. - tinst should be zero'ed out to not confuse previous mode when redirecting faults, otherwise the vector insn can be mistaken as a regular load/store. - VS in previous mode must be set dirty for loads. These will be addressed in follow-up patches. [1] https://github.com/ganboing/qemu/tree/ganboing-misalign [2] https://github.com/ganboing/qemu/tree/ganboing-misalign-no-tinst [3] https://github.com/ganboing/opensbi/tree/fix-ldst-v1 Bo Gan (7): include: sbi: Add more mstatus and instruction encoding include: sbi: Add sbi_regs_prev_xlen include: sbi: Add GET_RDS_NUM/SET(_FP32/_FP64)_RDS macros include: sbi: set FS dirty in vsstatus when V=1 lib: sbi: Do not override emulator callback for vector load/store lib: sbi: Rework load/store emulator instruction decoding [NOT-FOR-UPSTREAM] Test program for misaligned load/store include/sbi/riscv_encoding.h | 21 +- include/sbi/riscv_fp.h | 30 ++- include/sbi/sbi_platform.h | 92 ++++--- include/sbi/sbi_trap.h | 59 ++++ include/sbi/sbi_trap_ldst.h | 4 +- lib/sbi/sbi_trap_ldst.c | 502 ++++++++++++++++++++++++----------- lib/sbi/sbi_trap_v_ldst.c | 25 +- tests/ldst.S | 134 ++++++++++ tests/ldst.h | 170 ++++++++++++ tests/test-misaligned-ldst.c | 154 +++++++++++ 10 files changed, 986 insertions(+), 205 deletions(-) create mode 100644 tests/ldst.S create mode 100644 tests/ldst.h create mode 100644 tests/test-misaligned-ldst.c -- 2.34.1 -- opensbi mailing list opensbi@lists.infradead.org http://lists.infradead.org/mailman/listinfo/opensbi