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[103.95.112.190]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-35a030490b9sm7298892a91.17.2026.03.12.22.21.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Mar 2026 22:21:12 -0700 (PDT) From: Nicholas Piggin To: opensbi@lists.infradead.org Cc: Nicholas Piggin , Himanshu Chauhan Subject: [PATCH 17/18] dbtr: Heterogeneous access type matching for mcontrol triggers Date: Fri, 13 Mar 2026 15:19:46 +1000 Message-ID: <20260313051948.4017134-18-npiggin@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260313051948.4017134-1-npiggin@gmail.com> References: <20260313051948.4017134-1-npiggin@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260312_222114_739004_A5EB87EA X-CRM114-Status: GOOD ( 17.49 ) X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "opensbi" Errors-To: opensbi-bounces+opensbi=archiver.kernel.org@lists.infradead.org The Tenstorrent Ascalon core has a set of mcontrol6 triggers which can match load/store, and a set which can match execute. Detect access types supported in mc/mc6 triggers by writing 1 to load/store/access fields and reading back the result. Unsupported bits read back 0. Account for this capability when allocating HW triggers. Signed-off-by: Nicholas Piggin --- include/sbi/sbi_dbtr.h | 1 + lib/sbi/sbi_dbtr.c | 77 ++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 76 insertions(+), 2 deletions(-) diff --git a/include/sbi/sbi_dbtr.h b/include/sbi/sbi_dbtr.h index c0b9369e..16407f34 100644 --- a/include/sbi/sbi_dbtr.h +++ b/include/sbi/sbi_dbtr.h @@ -52,6 +52,7 @@ struct sbi_hw_trigger { unsigned long index; bool inuse; /* Allocated for a DBTR trigger */ unsigned long type_mask; /* Types supported by this trigger */ + unsigned long mcontrol_rwx_mask; /* rwx match bits supported */ }; struct sbi_dbtr_trigger { diff --git a/lib/sbi/sbi_dbtr.c b/lib/sbi/sbi_dbtr.c index f91a2b0d..f3186993 100644 --- a/lib/sbi/sbi_dbtr.c +++ b/lib/sbi/sbi_dbtr.c @@ -60,6 +60,15 @@ static unsigned long hart_state_ptr_offset; #define DBTR_SHMEM_MAKE_PHYS(_p_hi, _p_lo) (_p_lo) +/* + * MC and MC6 type and access fields are the same, no + * point duplicating this with MC vs MC6 accessors. + */ +#define RV_DBTR_MC_RWX_MASK \ + (RV_DBTR_BIT_MASK(MC, LOAD) | \ + RV_DBTR_BIT_MASK(MC, STORE) | \ + RV_DBTR_BIT_MASK(MC, EXEC)) + /* must call with hs != NULL */ static inline bool sbi_dbtr_shmem_disabled( struct sbi_dbtr_hart_triggers_state *hs) @@ -90,6 +99,19 @@ static bool sbi_hw_trigger_supports(struct sbi_hw_trigger *hw_trig, { if (!(BIT(type) & hw_trig->type_mask)) return false; + + switch (type) { + case RISCV_DBTR_TRIG_MCONTROL: + case RISCV_DBTR_TRIG_MCONTROL6: + if ((hw_trig->mcontrol_rwx_mask & tdata1) != (tdata1 & RV_DBTR_MC_RWX_MASK)) + return false; + break; + case RISCV_DBTR_TRIG_ICOUNT: + break; + default: + break; + } + return true; } @@ -180,6 +202,7 @@ static bool sbi_hw_trigger_probe(int i) { struct sbi_hw_trigger *hw_trig = INDEX_TO_HW_TRIGGER(i); struct sbi_trap_info trap = {0}; + unsigned long type; unsigned long tdata1; unsigned long val; @@ -204,8 +227,6 @@ static bool sbi_hw_trigger_probe(int i) val = csr_read_allowed(CSR_TINFO, &trap); if (trap.cause) { - unsigned long type; - /* * If reading tinfo caused an exception, the * debugger must read tdata1 to discover the @@ -227,6 +248,51 @@ static bool sbi_hw_trigger_probe(int i) hw_trig->type_mask = val; } + /* Probe supported features for each supported type */ + for (type = 0; type < 32; type++) { + if (!(hw_trig->type_mask & (1UL << type))) + continue; + csr_write(CSR_TDATA1, 0x0); + csr_write(CSR_TDATA2, 0x0); + + switch (type) { + case RISCV_DBTR_TRIG_MCONTROL: + case RISCV_DBTR_TRIG_MCONTROL6: + /* + * Set an MC/MC6 type trigger with load/store/exec bits + * set, then read which remain set. The implementation + * should read back zeroes for unsupported bits. + */ + tdata1 = RV_DBTR_MC_RWX_MASK; + RV_DBTR_SET_MC_TYPE(tdata1, type); + csr_write(CSR_TDATA1, tdata1); + tdata1 = csr_read(CSR_TDATA1); + if (TDATA1_GET_TYPE(tdata1) != type) { + sbi_printf("DBTR error: Hardware trigger type could not be set\n"); + /* Disable the trigger type */ + hw_trig->type_mask &= ~(1UL << type); + } + hw_trig->mcontrol_rwx_mask = tdata1 & RV_DBTR_MC_RWX_MASK; + if (hw_trig->mcontrol_rwx_mask == 0) { + sbi_printf("DBTR error: Hardware trigger type has no access bits\n"); + /* Disable the trigger type */ + hw_trig->type_mask &= ~(1UL << type); + } + + csr_write(CSR_TDATA1, 0x0); /* Reset tdata1 */ + break; + case RISCV_DBTR_TRIG_ICOUNT: + break; + default: + break; + } + } + + if (hw_trig->type_mask == 0) { + /* May get here if the above "impossible" conditions are hit */ + return false; + } + return true; } @@ -917,6 +983,13 @@ int sbi_dbtr_update_trig(unsigned long smode, err = SBI_ERR_INVALID_PARAM; goto out_unmap; } + + hw_trig = INDEX_TO_HW_TRIGGER(GET_TRIG_HW_INDEX(trig->state)); + if (!sbi_hw_trigger_supports(hw_trig, type, tdata1)) { + *out = _idx; + err = SBI_ERR_NOT_SUPPORTED; + goto out_unmap; + } } /* Update triggers */ -- 2.51.0 -- opensbi mailing list opensbi@lists.infradead.org http://lists.infradead.org/mailman/listinfo/opensbi