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* [PATCH v1 0/4] Add eager FP and RISC-V vector context switching support
@ 2026-03-20 14:23 dave.patel
  2026-03-20 14:23 ` [PATCH 1/4] lib: sbi: domain: ensure boot_hartid is assigned dave.patel
                   ` (3 more replies)
  0 siblings, 4 replies; 5+ messages in thread
From: dave.patel @ 2026-03-20 14:23 UTC (permalink / raw)
  To: opensbi
  Cc: Scott Bambrough, Robin Randhawa, Anup Patel, Samuel Holland,
	Dave Patel, Ray Mao, Anup Patel, Dhaval, Peter Lin

Hi,

This patch series adds support for eager floating-point and RISC-V vector
context save/restore in OpenSBI.

The goal is to ensure that machine-mode trap handling preserves the full
architectural state of lower privilege software (e.g., S-mode), providing
correct isolation across trap boundaries.

### Overview

This series introduces:

* Per-hart FP and vector context pointers in `sbi_scratch`
* FP context save/restore implementation
* RISC-V vector context save/restore implementation
* Integration into the OpenSBI trap handler

### Design

The implementation follows an eager context switching model:

* FP and vector state is saved on every trap entry
* FP and vector state is restored before returning from traps

This ensures correctness and avoids the need for lazy switching or
trap-on-first-use mechanisms.

### Context Storage

* FP context:

  * f0–f31 registers
  * fcsr

* Vector context:

  * v0–v31 registers
  * vl, vtype, vcsr

Stored per-hart via `sbi_scratch`.

### Notes / Assumptions

* Assumes FP and vector units are enabled when used (mstatus.FS/VS)
* Assumes RV64 for floating-point implementation (fsd/fld)
* Vector maximum size is bounded by SBI_MAX_VLENB
* Context pointers must be initialized before use

### Performance

This approach introduces additional overhead on every trap due to full
state save and restore, especially for vector state, but provides a
simple and deterministic model.

### Patch Breakdown

* Patch 1: Add FP context save/restore support
* Patch 2: Add vector context save/restore support
* Patch 3: Extend sbi_scratch with FP/vector context pointers
* Patch 4: Integrate into trap handler

Feedback is welcome, especially regarding:

* CSR restore ordering (vtype/vl/vcsr)
* Trap performance implications

Thanks,
Dave Patel


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^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH 1/4] lib: sbi: domain: ensure boot_hartid is assigned
  2026-03-20 14:23 [PATCH v1 0/4] Add eager FP and RISC-V vector context switching support dave.patel
@ 2026-03-20 14:23 ` dave.patel
  2026-03-20 14:23 ` [PATCH 2/4] lib: sbi: Add RISC-V vector context save/restore support (eager switching) dave.patel
                   ` (2 subsequent siblings)
  3 siblings, 0 replies; 5+ messages in thread
From: dave.patel @ 2026-03-20 14:23 UTC (permalink / raw)
  To: opensbi
  Cc: Scott Bambrough, Robin Randhawa, Anup Patel, Samuel Holland,
	Dave Patel, Ray Mao, Anup Patel, Dhaval, Peter Lin

From: Raymond Mao <raymond.mao@riscstar.com>

When boot_hartid points to a hart that is not in the domain's assigned
hartmask (e.g. due to cold boot hart differences), the domain startup
can skip starting the intended boot hart, leading to intermittent Linux
boot failures. Scan the assigned hartmask and pick the first available
hartid to guarantee a valid boot target.
---
 lib/sbi/sbi_domain.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c
index 4e8d2045..498a1d56 100644
--- a/lib/sbi/sbi_domain.c
+++ b/lib/sbi/sbi_domain.c
@@ -804,6 +804,30 @@ int sbi_domain_startup(struct sbi_scratch *scratch, u32 cold_hartid)
 
 	/* Startup boot HART of domains */
 	sbi_domain_for_each(dom) {
+		u32 boot_hartindex = sbi_hartid_to_hartindex(dom->boot_hartid);
+		bool boot_assigned = false;
+
+		if (sbi_hartindex_valid(boot_hartindex)) {
+			spin_lock(&dom->assigned_harts_lock);
+			boot_assigned = sbi_hartmask_test_hartindex(
+				boot_hartindex, &dom->assigned_harts);
+			spin_unlock(&dom->assigned_harts_lock);
+		}
+
+		if (!boot_assigned) {
+			u32 new_hartid = -1U;
+
+			spin_lock(&dom->assigned_harts_lock);
+			sbi_hartmask_for_each_hartindex(dhart, &dom->assigned_harts) {
+				new_hartid = sbi_hartindex_to_hartid(dhart);
+				break;
+			}
+			spin_unlock(&dom->assigned_harts_lock);
+
+			if (new_hartid != -1U)
+				dom->boot_hartid = new_hartid;
+		}
+
 		/* Domain boot HART index */
 		dhart = sbi_hartid_to_hartindex(dom->boot_hartid);
 
-- 
2.43.0


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^ permalink raw reply related	[flat|nested] 5+ messages in thread

* [PATCH 2/4] lib: sbi: Add RISC-V vector context save/restore support (eager switching)
  2026-03-20 14:23 [PATCH v1 0/4] Add eager FP and RISC-V vector context switching support dave.patel
  2026-03-20 14:23 ` [PATCH 1/4] lib: sbi: domain: ensure boot_hartid is assigned dave.patel
@ 2026-03-20 14:23 ` dave.patel
  2026-03-20 14:23 ` [PATCH 3/4] lib: sbi: Add floating-point context save/restore support dave.patel
  2026-03-20 14:23 ` [PATCH 4/4] include: sbi: scratch: Add per-hart FP and vector context pointers in scratch dave.patel
  3 siblings, 0 replies; 5+ messages in thread
From: dave.patel @ 2026-03-20 14:23 UTC (permalink / raw)
  To: opensbi
  Cc: Scott Bambrough, Robin Randhawa, Anup Patel, Samuel Holland,
	Dave Patel, Ray Mao, Anup Patel, Dhaval, Peter Lin

From: Dave Patel <dave.patel@riscstar.com>

Add support for saving and restoring RISC-V vector extension state in OpenSBI.
This introduces a per-hart vector context structure and helper routines to
perform full context save and restore.

The vector context includes vl, vtype, vcsr CSRs along with storage for all
32 vector registers. The register state is saved and restored using byte-wise
vector load/store instructions (vse8.v/vle8.v), making the implementation
independent of current SEW/LMUL configuration.

The implementation follows an eager context switching model where the entire
vector state is saved and restored on every context switch. This provides a
simple and deterministic mechanism without requiring lazy trap-based
management.

A per-hart pointer is used to track the current vector context owner.

Notes:
- The maximum supported VLEN is capped via SBI_MAX_VLENB.
- The implementation assumes the vector unit is enabled when invoked.
- vstart CSR is not currently saved/restored and is expected to be zero
across context switch boundaries.

Signed-off-by: Dave Patel <dave.patel@riscstar.com>
---
 include/sbi/sbi_vector.h |  30 +++++++++
 lib/sbi/objects.mk       |   1 +
 lib/sbi/sbi_vector.c     | 136 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 167 insertions(+)
 create mode 100644 include/sbi/sbi_vector.h
 create mode 100644 lib/sbi/sbi_vector.c

diff --git a/include/sbi/sbi_vector.h b/include/sbi/sbi_vector.h
new file mode 100644
index 00000000..6be477c0
--- /dev/null
+++ b/include/sbi/sbi_vector.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2026 RISCstar Solutions.
+ *
+ * Authors:
+ *     Dave Patel <dave.patel@riscstar.com>
+ */
+
+#ifndef __SBI_VECTOR_H__
+#define __SBI_VECTOR_H__
+
+#include <sbi/sbi_types.h>
+
+#define SBI_MAX_VLENB 256
+
+struct sbi_vector_context {
+    unsigned long vl;
+    unsigned long vtype;
+    unsigned long vcsr;
+
+    /* size depends on VLEN */
+    uint8_t vregs[32 * SBI_MAX_VLENB];
+};
+
+struct sbi_vector_context *sbi_current_vector_context(void);
+void sbi_vector_save(struct sbi_vector_context *dst);
+void sbi_vector_restore(const struct sbi_vector_context *src);
+
+#endif //__SBI_VECTOR_H__
+
diff --git a/lib/sbi/objects.mk b/lib/sbi/objects.mk
index ea816e92..5c0caf39 100644
--- a/lib/sbi/objects.mk
+++ b/lib/sbi/objects.mk
@@ -106,3 +106,4 @@ libsbi-objs-y += sbi_trap_v_ldst.o
 libsbi-objs-y += sbi_unpriv.o
 libsbi-objs-y += sbi_expected_trap.o
 libsbi-objs-y += sbi_cppc.o
+libsbi-objs-y += sbi_vector.o
diff --git a/lib/sbi/sbi_vector.c b/lib/sbi/sbi_vector.c
new file mode 100644
index 00000000..37239ce2
--- /dev/null
+++ b/lib/sbi/sbi_vector.c
@@ -0,0 +1,136 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2026 RISCstar Solutions.
+ *
+ * Authors:
+ *     Dave Patel <dave.patel@riscstar.com>
+ */
+
+#include <sbi/sbi_domain.h>
+#include <sbi/riscv_encoding.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/sbi_vector.h>
+
+/* Per-hart vector owner */
+static inline struct sbi_vector_context **vec_owner_ptr(void)
+{
+    struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
+    return &scratch->vec_ctx;
+}
+
+/* Get current vector context */
+struct sbi_vector_context *sbi_current_vector_context(void)
+{
+    return *vec_owner_ptr();
+}
+
+static inline unsigned long vector_vlenb(void)
+{
+    unsigned long vlenb;
+    asm volatile ("csrr %0, vlenb" : "=r"(vlenb));
+    return vlenb;
+}
+
+
+void sbi_vector_save(struct sbi_vector_context *dst)
+{
+    if (!dst)
+        return;
+
+    uint8_t *base = dst->vregs;
+    unsigned long vlenb = vector_vlenb();
+
+    asm volatile("csrr %0, vtype" : "=r"(dst->vtype));
+    asm volatile("csrr %0, vl" : "=r"(dst->vl));
+    asm volatile("csrr %0, vcsr" : "=r"(dst->vcsr));
+
+#define SAVE_VREG(num) \
+    asm volatile("vse8.v v" #num ", (%0)" :: "r"(base + num * vlenb) : "memory")
+
+    SAVE_VREG(0);
+    SAVE_VREG(1);
+    SAVE_VREG(2);
+    SAVE_VREG(3);
+    SAVE_VREG(4);
+    SAVE_VREG(5);
+    SAVE_VREG(6);
+    SAVE_VREG(7);
+    SAVE_VREG(8);
+    SAVE_VREG(9);
+    SAVE_VREG(10);
+    SAVE_VREG(11);
+    SAVE_VREG(12);
+    SAVE_VREG(13);
+    SAVE_VREG(14);
+    SAVE_VREG(15);
+    SAVE_VREG(16);
+    SAVE_VREG(17);
+    SAVE_VREG(18);
+    SAVE_VREG(19);
+    SAVE_VREG(20);
+    SAVE_VREG(21);
+    SAVE_VREG(22);
+    SAVE_VREG(23);
+    SAVE_VREG(24);
+    SAVE_VREG(25);
+    SAVE_VREG(26);
+    SAVE_VREG(27);
+    SAVE_VREG(28);
+    SAVE_VREG(29);
+    SAVE_VREG(30);
+    SAVE_VREG(31);
+
+#undef SAVE_VREG
+}
+
+void sbi_vector_restore(const struct sbi_vector_context *src)
+{
+    if (!src)
+        return;
+
+    const uint8_t *base = src->vregs;
+    unsigned long vlenb = vector_vlenb();
+
+    asm volatile("csrw vtype, %0" :: "r"(src->vtype));
+    asm volatile("csrw vl, %0" :: "r"(src->vl));
+    asm volatile("csrw vcsr, %0" :: "r"(src->vcsr));
+
+#define RESTORE_VREG(num) \
+    asm volatile("vle8.v v" #num ", (%0)" :: "r"(base + num * vlenb) : "memory")
+
+    RESTORE_VREG(0);
+    RESTORE_VREG(1);
+    RESTORE_VREG(2);
+    RESTORE_VREG(3);
+    RESTORE_VREG(4);
+    RESTORE_VREG(5);
+    RESTORE_VREG(6);
+    RESTORE_VREG(7);
+    RESTORE_VREG(8);
+    RESTORE_VREG(9);
+    RESTORE_VREG(10);
+    RESTORE_VREG(11);
+    RESTORE_VREG(12);
+    RESTORE_VREG(13);
+    RESTORE_VREG(14);
+    RESTORE_VREG(15);
+    RESTORE_VREG(16);
+    RESTORE_VREG(17);
+    RESTORE_VREG(18);
+    RESTORE_VREG(19);
+    RESTORE_VREG(20);
+    RESTORE_VREG(21);
+    RESTORE_VREG(22);
+    RESTORE_VREG(23);
+    RESTORE_VREG(24);
+    RESTORE_VREG(25);
+    RESTORE_VREG(26);
+    RESTORE_VREG(27);
+    RESTORE_VREG(28);
+    RESTORE_VREG(29);
+    RESTORE_VREG(30);
+    RESTORE_VREG(31);
+
+#undef RESTORE_VREG
+}
+
-- 
2.43.0


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^ permalink raw reply related	[flat|nested] 5+ messages in thread

* [PATCH 3/4] lib: sbi: Add floating-point context save/restore support.
  2026-03-20 14:23 [PATCH v1 0/4] Add eager FP and RISC-V vector context switching support dave.patel
  2026-03-20 14:23 ` [PATCH 1/4] lib: sbi: domain: ensure boot_hartid is assigned dave.patel
  2026-03-20 14:23 ` [PATCH 2/4] lib: sbi: Add RISC-V vector context save/restore support (eager switching) dave.patel
@ 2026-03-20 14:23 ` dave.patel
  2026-03-20 14:23 ` [PATCH 4/4] include: sbi: scratch: Add per-hart FP and vector context pointers in scratch dave.patel
  3 siblings, 0 replies; 5+ messages in thread
From: dave.patel @ 2026-03-20 14:23 UTC (permalink / raw)
  To: opensbi
  Cc: Scott Bambrough, Robin Randhawa, Anup Patel, Samuel Holland,
	Dave Patel, Ray Mao, Anup Patel, Dhaval, Peter Lin

From: Dave Patel <dave.patel@riscstar.com>

Add support for saving and restoring RISC-V floating-point (F/D) extension
state in OpenSBI. This introduces a per-hart floating-point context
structure and helper routines to perform full context save and restore.

The floating-point context includes storage for all 32 FPi registers (f0–f31)
along with the fcsr control and status register. The register state is saved
and restored using double-precision load/store instructions (fsd/fld),
assuming an RV64 system with D-extension support.

The implementation follows an eager context switching model where the entire
FP state is saved and restored on every context switch. This avoids the need
for trap-based lazy management and keeps the design simple and deterministic.

A per-hart pointer is used to track the current floating-point context owner.

Notes:
- The implementation assumes the floating-point unit is enabled
(mstatus.FS != Off) when invoked.
- The context layout is fixed to 64-bit FP registers.

Signed-off-by: Dave Patel <dave.patel@riscstar.com>"
---
 include/sbi/sbi_fp.h |  22 ++++++++
 lib/sbi/objects.mk   |   1 +
 lib/sbi/sbi_fp.c     | 117 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 140 insertions(+)
 create mode 100644 include/sbi/sbi_fp.h
 create mode 100644 lib/sbi/sbi_fp.c

diff --git a/include/sbi/sbi_fp.h b/include/sbi/sbi_fp.h
new file mode 100644
index 00000000..58c5b50e
--- /dev/null
+++ b/include/sbi/sbi_fp.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2026 RISCstar Solutions.
+ *
+ * Authors:
+ *     Dave Patel <dave.patel@riscstar.com>
+ */
+
+#ifndef __SBI_FP_H__
+#define __SBI_FP_H__
+
+struct sbi_fp_context {
+    unsigned long f[32];
+    unsigned long fcsr;
+};
+
+struct sbi_fp_context *sbi_current_fp_context(void);
+void sbi_fp_save(struct sbi_fp_context *dst);
+void sbi_fp_restore(const struct sbi_fp_context *src);
+
+#endif //__SBI_VECTOR_H__
+
diff --git a/lib/sbi/objects.mk b/lib/sbi/objects.mk
index 5c0caf39..ca560c2e 100644
--- a/lib/sbi/objects.mk
+++ b/lib/sbi/objects.mk
@@ -107,3 +107,4 @@ libsbi-objs-y += sbi_unpriv.o
 libsbi-objs-y += sbi_expected_trap.o
 libsbi-objs-y += sbi_cppc.o
 libsbi-objs-y += sbi_vector.o
+libsbi-objs-y += sbi_fp.o
diff --git a/lib/sbi/sbi_fp.c b/lib/sbi/sbi_fp.c
new file mode 100644
index 00000000..4d5e0f68
--- /dev/null
+++ b/lib/sbi/sbi_fp.c
@@ -0,0 +1,117 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2026 RISCstar Solutions.
+ *
+ * Authors:
+ *     Dave Patel <dave.patel@riscstar.com>
+ */
+
+#include <sbi/riscv_asm.h>
+#include <sbi/riscv_encoding.h>
+#include <sbi/sbi_scratch.h>
+#include <sbi/sbi_fp.h>
+
+/* Per-hart current owner pointer (SMP-safe) */
+static inline struct sbi_fp_context **fp_owner_ptr(void)
+{
+    struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
+    return &scratch->fp_ctx;
+}
+
+/* Get current FP context */
+struct sbi_fp_context *sbi_current_fp_context(void)
+{
+    return *fp_owner_ptr();
+}
+
+void sbi_fp_save(struct sbi_fp_context *dst)
+{
+	if (!dst)
+		return;
+
+	asm volatile(
+		"fsd f0,  0(%0)\n"
+		"fsd f1,  8(%0)\n"
+		"fsd f2, 16(%0)\n"
+		"fsd f3, 24(%0)\n"
+		"fsd f4, 32(%0)\n"
+		"fsd f5, 40(%0)\n"
+		"fsd f6, 48(%0)\n"
+		"fsd f7, 56(%0)\n"
+		"fsd f8, 64(%0)\n"
+		"fsd f9, 72(%0)\n"
+		"fsd f10, 80(%0)\n"
+		"fsd f11, 88(%0)\n"
+		"fsd f12, 96(%0)\n"
+		"fsd f13, 104(%0)\n"
+		"fsd f14, 112(%0)\n"
+		"fsd f15, 120(%0)\n"
+		"fsd f16, 128(%0)\n"
+		"fsd f17, 136(%0)\n"
+		"fsd f18, 144(%0)\n"
+		"fsd f19, 152(%0)\n"
+		"fsd f20, 160(%0)\n"
+		"fsd f21, 168(%0)\n"
+		"fsd f22, 176(%0)\n"
+		"fsd f23, 184(%0)\n"
+		"fsd f24, 192(%0)\n"
+		"fsd f25, 200(%0)\n"
+		"fsd f26, 208(%0)\n"
+		"fsd f27, 216(%0)\n"
+		"fsd f28, 224(%0)\n"
+		"fsd f29, 232(%0)\n"
+		"fsd f30, 240(%0)\n"
+		"fsd f31, 248(%0)\n"
+		:
+		: "r"(dst->f)
+		: "memory"
+	);
+
+	dst->fcsr = csr_read(CSR_FCSR);
+}
+
+void sbi_fp_restore(const struct sbi_fp_context *src)
+{
+    if (!src)
+        return;
+
+	asm volatile(
+		"fld f0,  0(%0)\n"
+		"fld f1,  8(%0)\n"
+		"fld f2, 16(%0)\n"
+		"fld f3, 24(%0)\n"
+		"fld f4, 32(%0)\n"
+		"fld f5, 40(%0)\n"
+		"fld f6, 48(%0)\n"
+		"fld f7, 56(%0)\n"
+		"fld f8, 64(%0)\n"
+		"fld f9, 72(%0)\n"
+		"fld f10, 80(%0)\n"
+		"fld f11, 88(%0)\n"
+		"fld f12, 96(%0)\n"
+		"fld f13, 104(%0)\n"
+		"fld f14, 112(%0)\n"
+		"fld f15, 120(%0)\n"
+		"fld f16, 128(%0)\n"
+		"fld f17, 136(%0)\n"
+		"fld f18, 144(%0)\n"
+		"fld f19, 152(%0)\n"
+		"fld f20, 160(%0)\n"
+		"fld f21, 168(%0)\n"
+		"fld f22, 176(%0)\n"
+		"fld f23, 184(%0)\n"
+		"fld f24, 192(%0)\n"
+		"fld f25, 200(%0)\n"
+		"fld f26, 208(%0)\n"
+		"fld f27, 216(%0)\n"
+		"fld f28, 224(%0)\n"
+		"fld f29, 232(%0)\n"
+		"fld f30, 240(%0)\n"
+		"fld f31, 248(%0)\n"
+		:
+		: "r"(src->f)
+		: "memory"
+	);
+
+	csr_write(CSR_FCSR, src->fcsr);
+}
-- 
2.43.0


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^ permalink raw reply related	[flat|nested] 5+ messages in thread

* [PATCH 4/4] include: sbi: scratch: Add per-hart FP and vector context pointers in scratch
  2026-03-20 14:23 [PATCH v1 0/4] Add eager FP and RISC-V vector context switching support dave.patel
                   ` (2 preceding siblings ...)
  2026-03-20 14:23 ` [PATCH 3/4] lib: sbi: Add floating-point context save/restore support dave.patel
@ 2026-03-20 14:23 ` dave.patel
  3 siblings, 0 replies; 5+ messages in thread
From: dave.patel @ 2026-03-20 14:23 UTC (permalink / raw)
  To: opensbi
  Cc: Scott Bambrough, Robin Randhawa, Anup Patel, Samuel Holland,
	Dave Patel, Ray Mao, Anup Patel, Dhaval, Peter Lin

From: Dave Patel <dave.patel@riscstar.com>

Extend the per-hart sbi_scratch structure to include pointers to floating-point
and vector context storage.

This enables tracking of the currently active FP and vector context on a per-hart
basis, which is required for eager context switching during trap handling.
The scratch structure serves as the central per-hart storage area, making these
pointers readily accessible in low-level trap and context switch paths.

The FP and vector context pointers are used by the corresponding save/restore
routines to preserve architectural state across traps, ensuring correct isolation
between privilege levels.

This change lays the foundation for eager FP and vector context management in OpenSBI.

Signed-off-by: Dave Patel <dave.patel@riscstar.com>
---
 include/sbi/sbi_scratch.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/include/sbi/sbi_scratch.h b/include/sbi/sbi_scratch.h
index 58d54628..13e4a294 100644
--- a/include/sbi/sbi_scratch.h
+++ b/include/sbi/sbi_scratch.h
@@ -54,6 +54,8 @@
 #ifndef __ASSEMBLER__
 
 #include <sbi/sbi_types.h>
+#include <sbi/sbi_fp.h>
+#include <sbi/sbi_vector.h>
 
 /** Representation of per-HART scratch space */
 struct sbi_scratch {
@@ -87,6 +89,9 @@ struct sbi_scratch {
 	unsigned long options;
 	/** Index of the hart */
 	unsigned long hartindex;
+    /* Current FP/Vector context owner per hart */
+    struct sbi_fp_context     *fp_ctx;
+    struct sbi_vector_context *vec_ctx;
 };
 
 /**
-- 
2.43.0


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end of thread, other threads:[~2026-03-20 14:24 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
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2026-03-20 14:23 [PATCH v1 0/4] Add eager FP and RISC-V vector context switching support dave.patel
2026-03-20 14:23 ` [PATCH 1/4] lib: sbi: domain: ensure boot_hartid is assigned dave.patel
2026-03-20 14:23 ` [PATCH 2/4] lib: sbi: Add RISC-V vector context save/restore support (eager switching) dave.patel
2026-03-20 14:23 ` [PATCH 3/4] lib: sbi: Add floating-point context save/restore support dave.patel
2026-03-20 14:23 ` [PATCH 4/4] include: sbi: scratch: Add per-hart FP and vector context pointers in scratch dave.patel

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