[PATCH v2 0/3] Add eager FP and RISC-V vector context switching support

From: dave.patel@riscstar.com
To: Samuel Holland <samuel.holland@sifive.com>
Cc: Scott Bambrough <scott@riscstar.com>,
	Robin Randhawa <robin.randhawa@sifive.com>,
	Anup Patel <anup.patel@qti.qualcomm.com>,
	Dave Patel <dave.patel@riscstar.com>,
	Ray Mao <raymond.mao@riscstar.com>,
	Anup Patel <anuppate@qti.qualcomm.com>,
	Dhaval <dhaval@rivosinc.com>, Peter Lin <peter.lin@sifive.com>,
	opensbi@lists.infradead.org
Subject: [PATCH v2 0/3] Add eager FP and RISC-V vector context switching support
Date: Thu, 26 Mar 2026 11:55:14 +0000	[thread overview]
Message-ID: <20260326115517.2156-1-dave.patel@riscstar.com> (raw)

Hi Samuel et. al,

Thanks you for the initial review and support, sending out v2 set of patch to gather
more consensus, currently the context switch itself in Opensbi is not being hooked up.

This series enhances OpenSBI domain context switching to properly save and restore
floating-point (FP) and vector (V) registers on multi-domain systems.

The context switch has now been corrected to the domain context switch instead of
trap handler; there is more understanding of how the one OS can context switch to
another OS for eg. Rich OS with Secure OS using Opensbi as monitor and that context
needs saving between the domain switch.

This eager context switching approach is more efficient as an alternative to lazy
context switch which cannot be used due to its limitation and is more efficient
to only store and restore on domain context switch.

This 3-patch series introduces:

1. **PATCH 1/3 – Domain data structure enhancements for Vector unit**
   - Adds domain pointers for Vector (`vec_ctx`) contexts.
   - Prepares the domain structure for storing isolated vector state.
   - Fixing compilation within each set of patch
   - Fixed all the assumptions
		--  added vstart CSR aswell for context switching.
		--  handled config based SBI_MAX_VLENB.
		--  Fixed vector support for Zve32x

2. **PATCH 2/3 – FP and Vector domain init/exit routines**
   - Adds domain pointers for FP (`fp_ctx`) contexts.
   - Prepares the domain structure for storing isolated vector state.
   - Fixing compilation within the patch and issue seen in v1 series.
   - Fixed all the assumptions
		-- added support for both 64 and 32 bit FP
		-- added support for double and single precision support.
		-- Support for correct context for Zve32x.
		-- removed dependencies on PLATFORM_RISCV_ISA=rv64gcv

3. **PATCH 3/3 – Domain context switch updates**
   - Updates `switch_to_next_domain_context()` to save and restore FP and vector
     registers.
   - Implements `sbi_fp_domain_init/exit` and `sbi_vector_domain_init/exit`.
   - Initializes FP/vector contexts during domain registration.
   - Cleans up context memory during shutdown.
   - Provides safe no-op versions for harts without FP or vector extensions.
   - Ensures FS and VS in `mstatus` are enabled only if Off.
   - Preserves original `mstatus` after restoring FP/vector state.
   - Works safely even on harts without FP or vector support.

Together, these changes ensure proper isolation of FP and vector registers between
domains, enabling robust multi-domain operation on RISC-V systems.

Signed-off-by: Dave Patel <dave.patel@riscstar.com>

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