[PATCH 0/4] irqchip/rpmi: Expose APLIC/IMSIC interfaces for platform use

[PATCH 0/4] irqchip/rpmi: Expose APLIC/IMSIC interfaces for platform use

[David E. Garcia Porras]

This series exposes existing APLIC and IMSIC internal definitions and
adds minimal extension points so that platform code can perform custom
interrupt configuration without modifying the generic irqchip drivers.

The motivation is that a platform which uses AIA may need to:
 - Configure APLIC source/target registers directly for M-mode
   interrupt routing
 - Iterate registered APLIC devices for platform-specific
   initialization
 - Handle M-mode external interrupts beyond IPI in the IMSIC driver
Furthermore, a platform using RPMI PERFORMANCE service group may
need to:
 - Use RPMI performance domain attribute flags for RPMI PERFORMANCE
   PERF_DOMAIN and FAST_CHANNEL attribute control

Patch 1 moves APLIC register defines from aplic.c to the public
aplic.h header (pure move, no functional change).
Patch 2 adds aplic_get_list() to allow platform code to iterate
registered APLIC devices.
Patch 3 routes non-IPI IMSIC interrupts through the sbi_irqchip
handler framework and adds hwirq_unmask/hwirq_mask callbacks so
that sbi_irqchip_register_handler() works end-to-end with IMSIC.
Patch 4 adds missing RPMI performance flag defines and a struct field.

All changes are additive and preserve existing behavior for platforms
that do not use the new interfaces.

David E. Garcia Porras (4):
  lib: utils: irqchip: aplic: Move register defines to public header
  lib: utils: irqchip: aplic: Add aplic_get_list() accessor
  lib: utils: irqchip: imsic: Dispatch non-IPI interrupts via irqchip
    framework
  include: mailbox: rpmi_msgprot: Add RPMI performance domain flag
    defines

 include/sbi_utils/irqchip/aplic.h        | 103 ++++++++++++++++++++++
 include/sbi_utils/mailbox/rpmi_msgprot.h |  18 ++++
 lib/utils/irqchip/aplic.c                | 106 ++---------------------
 lib/utils/irqchip/imsic.c                |  15 +++-
 4 files changed, 139 insertions(+), 103 deletions(-)

--
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[PATCH 1/4] lib: utils: irqchip: aplic: Move register defines to public header

[David E. Garcia Porras]

The APLIC register-level defines (DOMAINCFG, SOURCECFG, TARGET, SETIE,
CLRIE, IDC, MSICFG, etc.) are currently defined locally in aplic.c and
not accessible to platform code. Platform implementations that need
direct APLIC register access for custom interrupt configuration (e.g.
MSI-mode source/target setup) have no way to use the canonical defines.

Move these defines from aplic.c to the public aplic.h header so that
platform code can configure APLIC registers without duplicating magic
numbers. The defines match the RISC-V AIA specification. No functional
change.

Signed-off-by: David E. Garcia Porras <david.garcia@aheadcomputing.com>
---
 include/sbi_utils/irqchip/aplic.h | 101 ++++++++++++++++++++++++++++++
 lib/utils/irqchip/aplic.c         | 101 ------------------------------
 2 files changed, 101 insertions(+), 101 deletions(-)

diff --git a/include/sbi_utils/irqchip/aplic.h b/include/sbi_utils/irqchip/aplic.h
index 3461d1c7..286c8f94 100644
--- a/include/sbi_utils/irqchip/aplic.h
+++ b/include/sbi_utils/irqchip/aplic.h
@@ -14,6 +14,107 @@
 #include <sbi/sbi_types.h>
 #include <sbi/sbi_irqchip.h>
 
+#define APLIC_MAX_IDC			(1UL << 14)
+#define APLIC_MAX_SOURCE		1024
+
+#define APLIC_DOMAINCFG		0x0000
+#define APLIC_DOMAINCFG_IE		(1 << 8)
+#define APLIC_DOMAINCFG_DM		(1 << 2)
+#define APLIC_DOMAINCFG_BE		(1 << 0)
+
+#define APLIC_SOURCECFG_BASE		0x0004
+#define APLIC_SOURCECFG_D		(1 << 10)
+#define APLIC_SOURCECFG_CHILDIDX_MASK	0x000003ff
+#define APLIC_SOURCECFG_SM_MASK	0x00000007
+#define APLIC_SOURCECFG_SM_INACTIVE	0x0
+#define APLIC_SOURCECFG_SM_DETACH	0x1
+#define APLIC_SOURCECFG_SM_EDGE_RISE	0x4
+#define APLIC_SOURCECFG_SM_EDGE_FALL	0x5
+#define APLIC_SOURCECFG_SM_LEVEL_HIGH	0x6
+#define APLIC_SOURCECFG_SM_LEVEL_LOW	0x7
+
+#define APLIC_MMSICFGADDR		0x1bc0
+#define APLIC_MMSICFGADDRH		0x1bc4
+#define APLIC_SMSICFGADDR		0x1bc8
+#define APLIC_SMSICFGADDRH		0x1bcc
+
+#define APLIC_xMSICFGADDRH_L		(1UL << 31)
+#define APLIC_xMSICFGADDRH_HHXS_MASK	0x1f
+#define APLIC_xMSICFGADDRH_HHXS_SHIFT	24
+#define APLIC_xMSICFGADDRH_LHXS_MASK	0x7
+#define APLIC_xMSICFGADDRH_LHXS_SHIFT	20
+#define APLIC_xMSICFGADDRH_HHXW_MASK	0x7
+#define APLIC_xMSICFGADDRH_HHXW_SHIFT	16
+#define APLIC_xMSICFGADDRH_LHXW_MASK	0xf
+#define APLIC_xMSICFGADDRH_LHXW_SHIFT	12
+#define APLIC_xMSICFGADDRH_BAPPN_MASK	0xfff
+
+#define APLIC_xMSICFGADDR_PPN_SHIFT	12
+
+#define APLIC_xMSICFGADDR_PPN_HART(__lhxs) \
+	((1UL << (__lhxs)) - 1)
+
+#define APLIC_xMSICFGADDR_PPN_LHX_MASK(__lhxw) \
+	((1UL << (__lhxw)) - 1)
+#define APLIC_xMSICFGADDR_PPN_LHX_SHIFT(__lhxs) \
+	((__lhxs))
+#define APLIC_xMSICFGADDR_PPN_LHX(__lhxw, __lhxs) \
+	(APLIC_xMSICFGADDR_PPN_LHX_MASK(__lhxw) << \
+	 APLIC_xMSICFGADDR_PPN_LHX_SHIFT(__lhxs))
+
+#define APLIC_xMSICFGADDR_PPN_HHX_MASK(__hhxw) \
+	((1UL << (__hhxw)) - 1)
+#define APLIC_xMSICFGADDR_PPN_HHX_SHIFT(__hhxs) \
+	((__hhxs) + APLIC_xMSICFGADDR_PPN_SHIFT)
+#define APLIC_xMSICFGADDR_PPN_HHX(__hhxw, __hhxs) \
+	(APLIC_xMSICFGADDR_PPN_HHX_MASK(__hhxw) << \
+	 APLIC_xMSICFGADDR_PPN_HHX_SHIFT(__hhxs))
+
+#define APLIC_SETIP_BASE		0x1c00
+#define APLIC_SETIPNUM			0x1cdc
+
+#define APLIC_CLRIP_BASE		0x1d00
+#define APLIC_CLRIPNUM			0x1ddc
+
+#define APLIC_SETIE_BASE		0x1e00
+#define APLIC_SETIENUM			0x1edc
+
+#define APLIC_CLRIE_BASE		0x1f00
+#define APLIC_CLRIENUM			0x1fdc
+
+#define APLIC_SETIPNUM_LE		0x2000
+#define APLIC_SETIPNUM_BE		0x2004
+
+#define APLIC_TARGET_BASE		0x3004
+#define APLIC_TARGET_HART_IDX_SHIFT	18
+#define APLIC_TARGET_HART_IDX_MASK	0x3fff
+#define APLIC_TARGET_GUEST_IDX_SHIFT	12
+#define APLIC_TARGET_GUEST_IDX_MASK	0x3f
+#define APLIC_TARGET_IPRIO_MASK	0xff
+#define APLIC_TARGET_EIID_MASK	0x7ff
+
+#define APLIC_IDC_BASE			0x4000
+#define APLIC_IDC_SIZE			32
+
+#define APLIC_IDC_IDELIVERY		0x00
+
+#define APLIC_IDC_IFORCE		0x04
+
+#define APLIC_IDC_ITHRESHOLD		0x08
+
+#define APLIC_IDC_TOPI			0x18
+#define APLIC_IDC_TOPI_ID_SHIFT	16
+#define APLIC_IDC_TOPI_ID_MASK	0x3ff
+#define APLIC_IDC_TOPI_PRIO_MASK	0xff
+
+#define APLIC_IDC_CLAIMI		0x1c
+
+#define APLIC_DEFAULT_PRIORITY		1
+#define APLIC_DISABLE_IDELIVERY		0
+#define APLIC_ENABLE_IDELIVERY		1
+#define APLIC_DISABLE_ITHRESHOLD	1
+#define APLIC_ENABLE_ITHRESHOLD		0
+
 #define APLIC_MAX_DELEGATE	16
 
 struct aplic_msicfg_data {
diff --git a/lib/utils/irqchip/aplic.c b/lib/utils/irqchip/aplic.c
index ec69c82b..a20cecf2 100644
--- a/lib/utils/irqchip/aplic.c
+++ b/lib/utils/irqchip/aplic.c
@@ -14,107 +14,6 @@
 #include <sbi/sbi_error.h>
 #include <sbi_utils/irqchip/aplic.h>
 
-#define APLIC_MAX_IDC			(1UL << 14)
-#define APLIC_MAX_SOURCE		1024
-
-#define APLIC_DOMAINCFG		0x0000
-#define APLIC_DOMAINCFG_IE		(1 << 8)
-#define APLIC_DOMAINCFG_DM		(1 << 2)
-#define APLIC_DOMAINCFG_BE		(1 << 0)
-
-#define APLIC_SOURCECFG_BASE		0x0004
-#define APLIC_SOURCECFG_D		(1 << 10)
-#define APLIC_SOURCECFG_CHILDIDX_MASK	0x000003ff
-#define APLIC_SOURCECFG_SM_MASK	0x00000007
-#define APLIC_SOURCECFG_SM_INACTIVE	0x0
-#define APLIC_SOURCECFG_SM_DETACH	0x1
-#define APLIC_SOURCECFG_SM_EDGE_RISE	0x4
-#define APLIC_SOURCECFG_SM_EDGE_FALL	0x5
-#define APLIC_SOURCECFG_SM_LEVEL_HIGH	0x6
-#define APLIC_SOURCECFG_SM_LEVEL_LOW	0x7
-
-#define APLIC_MMSICFGADDR		0x1bc0
-#define APLIC_MMSICFGADDRH		0x1bc4
-#define APLIC_SMSICFGADDR		0x1bc8
-#define APLIC_SMSICFGADDRH		0x1bcc
-
-#define APLIC_xMSICFGADDRH_L		(1UL << 31)
-#define APLIC_xMSICFGADDRH_HHXS_MASK	0x1f
-#define APLIC_xMSICFGADDRH_HHXS_SHIFT	24
-#define APLIC_xMSICFGADDRH_LHXS_MASK	0x7
-#define APLIC_xMSICFGADDRH_LHXS_SHIFT	20
-#define APLIC_xMSICFGADDRH_HHXW_MASK	0x7
-#define APLIC_xMSICFGADDRH_HHXW_SHIFT	16
-#define APLIC_xMSICFGADDRH_LHXW_MASK	0xf
-#define APLIC_xMSICFGADDRH_LHXW_SHIFT	12
-#define APLIC_xMSICFGADDRH_BAPPN_MASK	0xfff
-
-#define APLIC_xMSICFGADDR_PPN_SHIFT	12
-
-#define APLIC_xMSICFGADDR_PPN_HART(__lhxs) \
-	((1UL << (__lhxs)) - 1)
-
-#define APLIC_xMSICFGADDR_PPN_LHX_MASK(__lhxw) \
-	((1UL << (__lhxw)) - 1)
-#define APLIC_xMSICFGADDR_PPN_LHX_SHIFT(__lhxs) \
-	((__lhxs))
-#define APLIC_xMSICFGADDR_PPN_LHX(__lhxw, __lhxs) \
-	(APLIC_xMSICFGADDR_PPN_LHX_MASK(__lhxw) << \
-	 APLIC_xMSICFGADDR_PPN_LHX_SHIFT(__lhxs))
-
-#define APLIC_xMSICFGADDR_PPN_HHX_MASK(__hhxw) \
-	((1UL << (__hhxw)) - 1)
-#define APLIC_xMSICFGADDR_PPN_HHX_SHIFT(__hhxs) \
-	((__hhxs) + APLIC_xMSICFGADDR_PPN_SHIFT)
-#define APLIC_xMSICFGADDR_PPN_HHX(__hhxw, __hhxs) \
-	(APLIC_xMSICFGADDR_PPN_HHX_MASK(__hhxw) << \
-	 APLIC_xMSICFGADDR_PPN_HHX_SHIFT(__hhxs))
-
-#define APLIC_SETIP_BASE		0x1c00
-#define APLIC_SETIPNUM			0x1cdc
-
-#define APLIC_CLRIP_BASE		0x1d00
-#define APLIC_CLRIPNUM			0x1ddc
-
-#define APLIC_SETIE_BASE		0x1e00
-#define APLIC_SETIENUM			0x1edc
-
-#define APLIC_CLRIE_BASE		0x1f00
-#define APLIC_CLRIENUM			0x1fdc
-
-#define APLIC_SETIPNUM_LE		0x2000
-#define APLIC_SETIPNUM_BE		0x2004
-
-#define APLIC_TARGET_BASE		0x3004
-#define APLIC_TARGET_HART_IDX_SHIFT	18
-#define APLIC_TARGET_HART_IDX_MASK	0x3fff
-#define APLIC_TARGET_GUEST_IDX_SHIFT	12
-#define APLIC_TARGET_GUEST_IDX_MASK	0x3f
-#define APLIC_TARGET_IPRIO_MASK	0xff
-#define APLIC_TARGET_EIID_MASK	0x7ff
-
-#define APLIC_IDC_BASE			0x4000
-#define APLIC_IDC_SIZE			32
-
-#define APLIC_IDC_IDELIVERY		0x00
-
-#define APLIC_IDC_IFORCE		0x04
-
-#define APLIC_IDC_ITHRESHOLD		0x08
-
-#define APLIC_IDC_TOPI			0x18
-#define APLIC_IDC_TOPI_ID_SHIFT	16
-#define APLIC_IDC_TOPI_ID_MASK	0x3ff
-#define APLIC_IDC_TOPI_PRIO_MASK	0xff
-
-#define APLIC_IDC_CLAIMI		0x1c
-
-#define APLIC_DEFAULT_PRIORITY		1
-#define APLIC_DISABLE_IDELIVERY		0
-#define APLIC_ENABLE_IDELIVERY		1
-#define APLIC_DISABLE_ITHRESHOLD	1
-#define APLIC_ENABLE_ITHRESHOLD		0
-
 static SBI_LIST_HEAD(aplic_list);
 static void aplic_writel_msicfg(struct aplic_msicfg_data *msicfg,
 				void *msicfgaddr, void *msicfgaddrH);
-- 
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[PATCH 2/4] lib: utils: irqchip: aplic: Add aplic_get_list() accessor

[David E. Garcia Porras]

The internal aplic_list is static, preventing platform code from
iterating over registered APLIC devices for custom configuration
(e.g. enabling domain-level interrupts in MSI delivery mode).

Add aplic_get_list() to return a pointer to the list head, allowing
platform code to walk registered APLIC devices without breaking
encapsulation by extern-ing the static list directly.

Signed-off-by: David E. Garcia Porras <david.garcia@aheadcomputing.com>
---
 include/sbi_utils/irqchip/aplic.h | 2 ++
 lib/utils/irqchip/aplic.c         | 5 +++++
 2 files changed, 7 insertions(+)

diff --git a/include/sbi_utils/irqchip/aplic.h b/include/sbi_utils/irqchip/aplic.h
index 286c8f94..e2cf5808 100644
--- a/include/sbi_utils/irqchip/aplic.h
+++ b/include/sbi_utils/irqchip/aplic.h
@@ -152,6 +152,8 @@ struct aplic_data {
 
 int aplic_cold_irqchip_init(struct aplic_data *aplic);
 
+struct sbi_dlist *aplic_get_list(void);
+
 void aplic_reinit_all(void);
 
 #endif
diff --git a/lib/utils/irqchip/aplic.c b/lib/utils/irqchip/aplic.c
index a20cecf2..ad9abf86 100644
--- a/lib/utils/irqchip/aplic.c
+++ b/lib/utils/irqchip/aplic.c
@@ -90,6 +90,11 @@ static void aplic_init(struct aplic_data *aplic)
 	}
 }
 
+struct sbi_dlist *aplic_get_list(void)
+{
+	return &aplic_list;
+}
+
 void aplic_reinit_all(void)
 {
 	struct aplic_data *aplic;
-- 
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[PATCH 3/4] lib: utils: irqchip: imsic: Dispatch non-IPI interrupts via irqchip framework

[David E. Garcia Porras]

Currently imsic_process_hwirqs() only handles the IPI interrupt
(IMSIC_IPI_ID) and logs all other external interrupts as unhandled.
Platforms using IMSIC in MSI delivery mode (APLIC wired to IMSIC)
have no way to handle M-mode external interrupts through the
existing sbi_irqchip handler registration framework.

Route non-IPI interrupts through sbi_irqchip_process_hwirq() so
that handlers registered via sbi_irqchip_register_handler() are
invoked. Also implement hwirq_unmask and hwirq_mask callbacks
using the existing imsic_local_eix_update() helper, enabling
sbi_irqchip_register_handler() to automatically enable interrupt
identities when a handler is registered.

Signed-off-by: David E. Garcia Porras <david.garcia@aheadcomputing.com>
---
 lib/utils/irqchip/imsic.c | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/lib/utils/irqchip/imsic.c b/lib/utils/irqchip/imsic.c
index 7559a069..6fd82688 100644
--- a/lib/utils/irqchip/imsic.c
+++ b/lib/utils/irqchip/imsic.c
@@ -159,8 +159,7 @@ static int imsic_process_hwirqs(struct sbi_irqchip_device *chip)
 			sbi_ipi_process();
 			break;
 		default:
-			sbi_printf("%s: unhandled IRQ%d\n",
-				   __func__, (u32)mirq);
+			sbi_irqchip_process_hwirq(chip, mirq);
 			break;
 		}
 	}
@@ -353,10 +352,22 @@ static int imsic_hwirq_setup(struct sbi_irqchip_device *chip, u32 hwirq)
 	return 0;
 }
 
+static void imsic_hwirq_unmask(struct sbi_irqchip_device *chip, u32 hwirq)
+{
+	imsic_local_eix_update(hwirq, 1, false, true);
+}
+
+static void imsic_hwirq_mask(struct sbi_irqchip_device *chip, u32 hwirq)
+{
+	imsic_local_eix_update(hwirq, 1, false, false);
+}
+
 static struct sbi_irqchip_device imsic_device = {
 	.warm_init	= imsic_warm_irqchip_init,
 	.process_hwirqs	= imsic_process_hwirqs,
 	.hwirq_setup	= imsic_hwirq_setup,
+	.hwirq_unmask	= imsic_hwirq_unmask,
+	.hwirq_mask	= imsic_hwirq_mask,
 };
 
 int imsic_cold_irqchip_init(struct imsic_data *imsic)
-- 
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[PATCH 4/4] include: mailbox: rpmi_msgprot: Add RPMI performance domain flag defines

[David E. Garcia Porras]

Add bit-field defines for the RPMI performance domain attributes flags
and fast-channel attributes flags as specified in the RPMI specification.
These are needed by platform implementations that provide RPMI
performance services (e.g. DVFS controllers).

Also add the missing db_write_value field to
rpmi_perf_get_fast_chn_attr_resp to match the RPMI spec layout.

Signed-off-by: David E. Garcia Porras <david.garcia@aheadcomputing.com>
---
 include/sbi_utils/mailbox/rpmi_msgprot.h | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/include/sbi_utils/mailbox/rpmi_msgprot.h b/include/sbi_utils/mailbox/rpmi_msgprot.h
index f8b16753..7ce1ca9f 100644
--- a/include/sbi_utils/mailbox/rpmi_msgprot.h
+++ b/include/sbi_utils/mailbox/rpmi_msgprot.h
@@ -830,6 +830,23 @@ struct rpmi_dpwr_get_state_resp {
 	u32 state;
 };
 
+#define RPMI_PERF_DOMAIN_ATTRS_FLAGS_MASK (7U << 0)
+#define RPMI_PERF_DOMAIN_ATTRS_FLAGS_FASTCHANNEL_SUPP_POS 0
+#define RPMI_PERF_DOMAIN_ATTRS_FLAGS_PERF_LVL_CHG_SUPP_POS 1
+#define RPMI_PERF_DOMAIN_ATTRS_FLAGS_PERF_LIMIT_CHG_SUPP_POS 2
+#define RPMI_PERF_DOMAIN_ATTRS_FLAGS_FASTCHANNEL_SUPP (1U << RPMI_PERF_DOMAIN_ATTRS_FLAGS_FASTCHANNEL_SUPP_POS)
+#define RPMI_PERF_DOMAIN_ATTRS_FLAGS_PERF_LVL_CHG_SUPP (1U << RPMI_PERF_DOMAIN_ATTRS_FLAGS_PERF_LVL_CHG_SUPP_POS)
+#define RPMI_PERF_DOMAIN_ATTRS_FLAGS_PERF_LIMIT_CHG_SUPP (1U << RPMI_PERF_DOMAIN_ATTRS_FLAGS_PERF_LIMIT_CHG_SUPP_POS)
+
+#define RPMI_PERF_FASTCHAN_ATTRS_FLAGS_MASK (7U << 0)
+#define RPMI_PERF_FASTCHAN_ATTRS_FLAGS_DB_SUPP_POS 0
+#define RPMI_PERF_FASTCHAN_ATTRS_FLAGS_DB_WIDTH_POS 1
+#define RPMI_PERF_FASTCHAN_ATTRS_FLAGS_DB_SUPP (1U << RPMI_PERF_FASTCHAN_ATTRS_FLAGS_DB_SUPP_POS)
+#define RPMI_PERF_FASTCHAN_ATTRS_FLAGS_DB_WIDTH_MASK (3U << RPMI_PERF_FASTCHAN_ATTRS_FLAGS_DB_WIDTH_POS)
+#define RPMI_PERF_FASTCHAN_ATTRS_FLAGS_DB_WIDTH_8 (0U << RPMI_PERF_FASTCHAN_ATTRS_FLAGS_DB_WIDTH_POS)
+#define RPMI_PERF_FASTCHAN_ATTRS_FLAGS_DB_WIDTH_16 (1U << RPMI_PERF_FASTCHAN_ATTRS_FLAGS_DB_WIDTH_POS)
+#define RPMI_PERF_FASTCHAN_ATTRS_FLAGS_DB_WIDTH_32 (2U << RPMI_PERF_FASTCHAN_ATTRS_FLAGS_DB_WIDTH_POS)
+
 /** RPMI Performance ServiceGroup Service IDs */
 enum rpmi_performance_service_id {
 	RPMI_PERF_SRV_ENABLE_NOTIFICATION = 0x01,
@@ -941,6 +958,7 @@ struct rpmi_perf_get_fast_chn_attr_resp {
 	u32 region_size;
 	u32 db_addr_low;
 	u32 db_addr_high;
+	u32 db_write_value;
 	u32 db_id_low;
 	u32 db_id_high;
 	u32 db_perserved_low;
-- 
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