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From: dave.patel@riscstar.com
To: Samuel Holland <samuel.holland@sifive.com>
Cc: Scott Bambrough <scott@riscstar.com>,
	Robin Randhawa <robin.randhawa@sifive.com>,
	Anup Patel <anup.patel@qti.qualcomm.com>,
	Dave Patel <dave.patel@riscstar.com>,
	Ray Mao <raymond.mao@riscstar.com>,
	Anup Patel <anuppate@qti.qualcomm.com>,
	Dhaval <dhaval@rivosinc.com>, Peter Lin <peter.lin@sifive.com>,
	opensbi@lists.infradead.org
Subject: [PATCH v3 2/3] lib: sbi: Add floating-point context save/restore support.
Date: Tue, 31 Mar 2026 06:58:56 +0100	[thread overview]
Message-ID: <20260331055858.305207-3-dave.patel@riscstar.com> (raw)
In-Reply-To: <20260331055858.305207-1-dave.patel@riscstar.com>

From: Dave Patel <dave.patel@riscstar.com>

Add support for saving and restoring RISC-V floating-point (F/D) extension
state in OpenSBI. This introduces a floating-point context structure and
helper routines to perform full context save and restore.

The floating-point context includes storage for all 32 FPi registers (f0–f31)
along with the fcsr control and status register. The register state is saved
and restored using double-precision load/store instructions (fsd/fld), and
single-precision load/store instructions (fsw/flw) on an RV64 system with
F and D-extension support.

The implementation follows an eager context switching model where the entire
FP state is saved and restored on every context switch. This avoids the need
for trap-based lazy management and keeps the design simple and deterministic.

Signed-off-by: Dave Patel <dave.patel@riscstar.com>"
---
 include/sbi/sbi_fp.h |  36 ++++++++
 lib/sbi/objects.mk   |   1 +
 lib/sbi/sbi_fp.c     | 191 +++++++++++++++++++++++++++++++++++++++++++
 lib/sbi/sbi_vector.c |  24 +++---
 4 files changed, 240 insertions(+), 12 deletions(-)
 create mode 100644 include/sbi/sbi_fp.h
 create mode 100644 lib/sbi/sbi_fp.c

diff --git a/include/sbi/sbi_fp.h b/include/sbi/sbi_fp.h
new file mode 100644
index 00000000..8079bb3b
--- /dev/null
+++ b/include/sbi/sbi_fp.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2026 RISCstar Solutions.
+ *
+ * Authors:
+ *   Dave Patel <dave.patel@riscstar.com>
+ */
+#ifndef __SBI_FP_H__
+#define __SBI_FP_H__
+
+#include <sbi/riscv_encoding.h>
+#include <sbi/sbi_types.h>
+
+#if defined(__riscv_f) || defined(__riscv_d)
+
+#include <stdint.h>
+
+struct sbi_fp_context {
+#if __riscv_d
+	uint64_t f[32];
+#else
+	uint32_t f[32];
+#endif
+	uint32_t fcsr;
+} __aligned(16);
+
+#else /* No FP (e.g., Zve32x) */
+
+struct sbi_fp_context { };
+
+#endif //defined(__riscv_f) || defined(__riscv_d)
+
+void sbi_fp_save(struct sbi_fp_context *dst);
+void sbi_fp_restore(const struct sbi_fp_context *src);
+
+#endif //__SBI_VECTOR_H__
diff --git a/lib/sbi/objects.mk b/lib/sbi/objects.mk
index 5c0caf39..ca560c2e 100644
--- a/lib/sbi/objects.mk
+++ b/lib/sbi/objects.mk
@@ -107,3 +107,4 @@ libsbi-objs-y += sbi_unpriv.o
 libsbi-objs-y += sbi_expected_trap.o
 libsbi-objs-y += sbi_cppc.o
 libsbi-objs-y += sbi_vector.o
+libsbi-objs-y += sbi_fp.o
diff --git a/lib/sbi/sbi_fp.c b/lib/sbi/sbi_fp.c
new file mode 100644
index 00000000..5d72b72e
--- /dev/null
+++ b/lib/sbi/sbi_fp.c
@@ -0,0 +1,191 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2026 RISCstar Solutions.
+ *
+ * Authors:
+ *   Dave Patel <dave.patel@riscstar.com>
+ */
+
+#include <sbi/riscv_asm.h>
+#include <sbi/riscv_encoding.h>
+#include <sbi/sbi_fp.h>
+
+#if defined(__riscv_f) || defined(__riscv_d)
+
+void sbi_fp_save(struct sbi_fp_context *dst)
+{
+	if (!dst)
+		return;
+
+#if defined(__riscv_d)
+	asm volatile(
+		"fsd f0,  0(%0)\n"
+		"fsd f1,  8(%0)\n"
+		"fsd f2,  16(%0)\n"
+		"fsd f3,  24(%0)\n"
+		"fsd f4,  32(%0)\n"
+		"fsd f5,  40(%0)\n"
+		"fsd f6,  48(%0)\n"
+		"fsd f7,  56(%0)\n"
+		"fsd f8,  64(%0)\n"
+		"fsd f9,  72(%0)\n"
+		"fsd f10, 80(%0)\n"
+		"fsd f11, 88(%0)\n"
+		"fsd f12, 96(%0)\n"
+		"fsd f13, 104(%0)\n"
+		"fsd f14, 112(%0)\n"
+		"fsd f15, 120(%0)\n"
+		"fsd f16, 128(%0)\n"
+		"fsd f17, 136(%0)\n"
+		"fsd f18, 144(%0)\n"
+		"fsd f19, 152(%0)\n"
+		"fsd f20, 160(%0)\n"
+		"fsd f21, 168(%0)\n"
+		"fsd f22, 176(%0)\n"
+		"fsd f23, 184(%0)\n"
+		"fsd f24, 192(%0)\n"
+		"fsd f25, 200(%0)\n"
+		"fsd f26, 208(%0)\n"
+		"fsd f27, 216(%0)\n"
+		"fsd f28, 224(%0)\n"
+		"fsd f29, 232(%0)\n"
+		"fsd f30, 240(%0)\n"
+		"fsd f31, 248(%0)\n"
+		:
+		: "r"(dst->f)
+		: "memory"
+	);
+#else
+	asm volatile(
+		"fsw f0,  0(%0)\n"
+		"fsw f1,  4(%0)\n"
+		"fsw f2,  8(%0)\n"
+		"fsw f3,  12(%0)\n"
+		"fsw f4,  16(%0)\n"
+		"fsw f5,  20(%0)\n"
+		"fsw f6,  24(%0)\n"
+		"fsw f7,  28(%0)\n"
+		"fsw f8,  32(%0)\n"
+		"fsw f9,  36(%0)\n"
+		"fsw f10, 40(%0)\n"
+		"fsw f11, 44(%0)\n"
+		"fsw f12, 48(%0)\n"
+		"fsw f13, 52(%0)\n"
+		"fsw f14, 56(%0)\n"
+		"fsw f15, 60(%0)\n"
+		"fsw f16, 64(%0)\n"
+		"fsw f17, 68(%0)\n"
+		"fsw f18, 72(%0)\n"
+		"fsw f19, 76(%0)\n"
+		"fsw f20, 80(%0)\n"
+		"fsw f21, 84(%0)\n"
+		"fsw f22, 88(%0)\n"
+		"fsw f23, 92(%0)\n"
+		"fsw f24, 96(%0)\n"
+		"fsw f25, 100(%0)\n"
+		"fsw f26, 104(%0)\n"
+		"fsw f27, 108(%0)\n"
+		"fsw f28, 112(%0)\n"
+		"fsw f29, 116(%0)\n"
+		"fsw f30, 120(%0)\n"
+		"fsw f31, 124(%0)\n"
+		:
+		: "r"(dst->f)
+		: "memory"
+	);
+#endif //__riscv_d
+
+	dst->fcsr = csr_read(CSR_FCSR);
+}
+
+void sbi_fp_restore(const struct sbi_fp_context *src)
+{
+	if (!src)
+		return;
+
+#if defined(__riscv_d)
+	asm volatile(
+		"fld f0,  0(%0)\n"
+		"fld f1,  8(%0)\n"
+		"fld f2,  16(%0)\n"
+		"fld f3,  24(%0)\n"
+		"fld f4,  32(%0)\n"
+		"fld f5,  40(%0)\n"
+		"fld f6,  48(%0)\n"
+		"fld f7,  56(%0)\n"
+		"fld f8,  64(%0)\n"
+		"fld f9,  72(%0)\n"
+		"fld f10, 80(%0)\n"
+		"fld f11, 88(%0)\n"
+		"fld f12, 96(%0)\n"
+		"fld f13, 104(%0)\n"
+		"fld f14, 112(%0)\n"
+		"fld f15, 120(%0)\n"
+		"fld f16, 128(%0)\n"
+		"fld f17, 136(%0)\n"
+		"fld f18, 144(%0)\n"
+		"fld f19, 152(%0)\n"
+		"fld f20, 160(%0)\n"
+		"fld f21, 168(%0)\n"
+		"fld f22, 176(%0)\n"
+		"fld f23, 184(%0)\n"
+		"fld f24, 192(%0)\n"
+		"fld f25, 200(%0)\n"
+		"fld f26, 208(%0)\n"
+		"fld f27, 216(%0)\n"
+		"fld f28, 224(%0)\n"
+		"fld f29, 232(%0)\n"
+		"fld f30, 240(%0)\n"
+		"fld f31, 248(%0)\n"
+		:
+		: "r"(src->f)
+		: "memory"
+	);
+#else
+
+	asm volatile(
+		"flw f0,   0(%0)\n"
+		"flw f1,   4(%0)\n"
+		"flw f2,   8(%0)\n"
+		"flw f3,  12(%0)\n"
+		"flw f4,  16(%0)\n"
+		"flw f5,  20(%0)\n"
+		"flw f6,  24(%0)\n"
+		"flw f7,  28(%0)\n"
+		"flw f8,  32(%0)\n"
+		"flw f9,  36(%0)\n"
+		"flw f10, 40(%0)\n"
+		"flw f11, 44(%0)\n"
+		"flw f12, 48(%0)\n"
+		"flw f13, 52(%0)\n"
+		"flw f14, 56(%0)\n"
+		"flw f15, 60(%0)\n"
+		"flw f16, 64(%0)\n"
+		"flw f17, 68(%0)\n"
+		"flw f18, 72(%0)\n"
+		"flw f19, 76(%0)\n"
+		"flw f20, 80(%0)\n"
+		"flw f21, 84(%0)\n"
+		"flw f22, 88(%0)\n"
+		"flw f23, 92(%0)\n"
+		"flw f24, 96(%0)\n"
+		"flw f25, 100(%0)\n"
+		"flw f26, 104(%0)\n"
+		"flw f27, 108(%0)\n"
+		"flw f28, 112(%0)\n"
+		"flw f29, 116(%0)\n"
+		"flw f30, 120(%0)\n"
+		"flw f31, 124(%0)\n"
+		:
+		: "r"(src->f)
+		: "memory"
+	);
+
+#endif
+
+	csr_write(CSR_FCSR, src->fcsr);
+}
+#else
+void sbi_fp_save(struct sbi_fp_context *dst) {}
+void sbi_fp_restore(const struct sbi_fp_context *src) {}
+#endif // FP present
diff --git a/lib/sbi/sbi_vector.c b/lib/sbi/sbi_vector.c
index 497d7f94..5a3f34d7 100644
--- a/lib/sbi/sbi_vector.c
+++ b/lib/sbi/sbi_vector.c
@@ -50,8 +50,8 @@ void sbi_vector_save(struct sbi_vector_context *dst)
 	if (!dst)
 		return;

-#define READ_CSR(dst, csr) (				\
-	do {						\
+#define READ_CSR(dst, csr) 				\
+	{						\
 		asm volatile(				\
 			"	.option push\n\t"	\
 			"	.option arch, +v\n\t"	\
@@ -60,7 +60,7 @@ void sbi_vector_save(struct sbi_vector_context *dst)
 			:	"=r"(dst)		\
 			:				\
 			:	"memory");		\
-	} while (0))
+	}

 	/* Step 1: Save CSRs */
 	READ_CSR(dst->vtype,  vtype);
@@ -80,13 +80,13 @@ void sbi_vector_save(struct sbi_vector_context *dst)
 	uint8_t *base = dst->vregs;

 	/* Step 3: Save vector registers */
-#define SAVE_VREG(i) (						\
-	asm volatile(						\
+#define SAVE_VREG(i) 						\
+	{asm volatile(						\
 		"	.option push\n\t"			\
 		"	.option arch, +v\n\t"			\
 		"	vse8.v v" #i ", (%0)\n\t"		\
 		"	.option pop\n\t"			\
-		::	"r"(base + (i) * vlenb)	: "memory"))
+		::	"r"(base + (i) * vlenb)	: "memory"); }

 	SAVE_VREG(0);
 	SAVE_VREG(1);
@@ -139,13 +139,13 @@ void sbi_vector_restore(const struct sbi_vector_context *src)
 	vsetvl(src->vl, src->vtype);

 	/* Step 2: Restore vector registers */
-#define RESTORE_VREG(i) (					\
-	asm volatile(						\
+#define RESTORE_VREG(i) 					\
+	{asm volatile(						\
 		"	.option push\n\t"			\
 		"	.option arch, +v\n\t"			\
 		"	vle8.v v" #i ", (%0)\n\t"		\
 		"	.option pop\n\t"			\
-		::	"r"(base + (i) * vlenb) : "memory"))
+		::	"r"(base + (i) * vlenb) : "memory"); }

 	RESTORE_VREG(0);
 	RESTORE_VREG(1);
@@ -182,15 +182,15 @@ void sbi_vector_restore(const struct sbi_vector_context *src)
 #undef RESTORE_VREG

 	/* Step 3: Restore CSR's last */
-#define WRITE_CSR(csr, val) (			\
-	asm volatile(				\
+#define WRITE_CSR(csr, val) 			\
+	{ asm volatile(				\
 		"	.option push\n\t"	\
 		"	.option arch, +v\n\t"	\
 		"	csrw " #csr ", %0\n\t"	\
 		"	.option pop\n\t"	\
 		:				\
 		:	"r"(val)		\
-		:	"memory"))
+		:	"memory"); }

 	/* Restore CSRs first */
 	WRITE_CSR(vtype,  src->vtype);
--
2.43.0


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  parent reply	other threads:[~2026-03-31  5:59 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-31  5:58 [PATCH v3 0/3] Add eager FP and RISC-V vector context switching support dave.patel
2026-03-31  5:58 ` [PATCH v3 1/3] lib: sbi: Add RISC-V vector context save/restore support dave.patel
2026-04-02 13:35   ` Radim Krčmář
2026-03-31  5:58 ` dave.patel [this message]
2026-04-02 13:40   ` [PATCH v3 2/3] lib: sbi: Add floating-point " Radim Krčmář
2026-03-31  5:58 ` [PATCH v3 3/3] lib: sbi: domain FP/Vector context support for context switch dave.patel
2026-04-02 13:54   ` Radim Krčmář
  -- strict thread matches above, loose matches on Subject: below --
2026-03-27 17:15 [PATCH v3 0/3] Add eager FP and RISC-V vector context switching support dave.patel
2026-03-27 17:16 ` [PATCH v3 2/3] lib: sbi: Add floating-point context save/restore support dave.patel

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