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Wed, 29 Apr 2026 21:56:00 -0700 (PDT) Received: from localhost ([124.158.97.178]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-834ed59fd4bsm3478563b3a.5.2026.04.29.21.55.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Apr 2026 21:55:59 -0700 (PDT) From: Nicholas Piggin To: opensbi@lists.infradead.org Cc: Nicholas Piggin Subject: [PATCH 4/7] lib: sbi: Add PMP CSR read and write accessors Date: Thu, 30 Apr 2026 14:55:22 +1000 Message-ID: <20260430045528.420437-6-npiggin@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260430045528.420437-1-npiggin@gmail.com> References: <20260430045528.420437-1-npiggin@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260429_215602_231166_7E8AA87E X-CRM114-Status: GOOD ( 14.16 ) X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "opensbi" Errors-To: opensbi-bounces+opensbi=archiver.kernel.org@lists.infradead.org PMPCFG CSR access is non-trivial as it requires shifting and masking, it makes PMP manipulation code simpler if this basic CSR read/write access is abstracted away. Signed-off-by: Nicholas Piggin --- lib/sbi/riscv_asm.c | 114 ++++++++++++++++++++++---------------------- 1 file changed, 58 insertions(+), 56 deletions(-) diff --git a/lib/sbi/riscv_asm.c b/lib/sbi/riscv_asm.c index 9b45805c..2fb0f585 100644 --- a/lib/sbi/riscv_asm.c +++ b/lib/sbi/riscv_asm.c @@ -273,14 +273,16 @@ void csr_write_num(int csr_num, unsigned long val) #undef switchcase_csr_write } -int pmp_disable(unsigned int n) +static int hart_pmp_read(pmp_t *pmp, unsigned int n) { - int pmpcfg_csr, pmpcfg_shift; - unsigned long cfgmask, pmpcfg; + int pmpcfg_csr, pmpcfg_shift, pmpaddr_csr; + unsigned long cfgmask; + /* check parameters */ if (n >= PMP_COUNT) return SBI_EINVAL; + /* calculate PMP register and offset */ #if __riscv_xlen == 32 pmpcfg_csr = CSR_PMPCFG0 + (n >> 2); pmpcfg_shift = (n & 3) << 3; @@ -290,48 +292,24 @@ int pmp_disable(unsigned int n) #else # error "Unexpected __riscv_xlen" #endif + pmpaddr_csr = CSR_PMPADDR0 + n; - /* Clear the address matching bits to disable the pmp entry */ - cfgmask = ~(0xffUL << pmpcfg_shift); - pmpcfg = (csr_read_num(pmpcfg_csr) & cfgmask); - - csr_write_num(pmpcfg_csr, pmpcfg); + cfgmask = (0xffUL << pmpcfg_shift); + pmp->cfg = (csr_read_num(pmpcfg_csr) & cfgmask) >> pmpcfg_shift; + pmp->addr = csr_read_num(pmpaddr_csr); return SBI_OK; } -int is_pmp_entry_mapped(unsigned long entry) -{ - unsigned long prot; - unsigned long addr; - unsigned long log2len; - - if (pmp_get(entry, &prot, &addr, &log2len) != 0) - return false; - - /* If address matching bits are non-zero, the entry is enable */ - if (prot & PMP_A) - return true; - - return false; -} - -int pmp_set(unsigned int n, unsigned long prot, unsigned long addr, - unsigned long log2len) +static int hart_pmp_write(pmp_t *pmp, unsigned int n) { int pmpcfg_csr, pmpcfg_shift, pmpaddr_csr; unsigned long cfgmask, pmpcfg; - pmp_t pmp; - int rc; /* check parameters */ if (n >= PMP_COUNT) return SBI_EINVAL; - rc = pmp_encode(&pmp, prot, addr, log2len); - if (rc) - return rc; - /* calculate PMP register and offset */ #if __riscv_xlen == 32 pmpcfg_csr = CSR_PMPCFG0 + (n >> 2); @@ -345,41 +323,65 @@ int pmp_set(unsigned int n, unsigned long prot, unsigned long addr, pmpaddr_csr = CSR_PMPADDR0 + n; /* write csrs */ - csr_write_num(pmpaddr_csr, pmp.addr); + csr_write_num(pmpaddr_csr, pmp->addr); cfgmask = ~(0xffUL << pmpcfg_shift); pmpcfg = (csr_read_num(pmpcfg_csr) & cfgmask); - pmpcfg |= (((unsigned long)pmp.cfg << pmpcfg_shift) & ~cfgmask); + pmpcfg |= (((unsigned long)pmp->cfg << pmpcfg_shift) & ~cfgmask); csr_write_num(pmpcfg_csr, pmpcfg); - return 0; + return SBI_OK; } -int pmp_get(unsigned int n, unsigned long *prot_out, unsigned long *addr_out, - unsigned long *log2len) +int pmp_disable(unsigned int n) { - int pmpcfg_csr, pmpcfg_shift, pmpaddr_csr; - unsigned long cfgmask; pmp_t pmp; + int rc; - /* check parameters */ - if (n >= PMP_COUNT) - return SBI_EINVAL; + rc = hart_pmp_read(&pmp, n); + if (rc) + return rc; - /* calculate PMP register and offset */ -#if __riscv_xlen == 32 - pmpcfg_csr = CSR_PMPCFG0 + (n >> 2); - pmpcfg_shift = (n & 3) << 3; -#elif __riscv_xlen == 64 - pmpcfg_csr = (CSR_PMPCFG0 + (n >> 2)) & ~1; - pmpcfg_shift = (n & 7) << 3; -#else -# error "Unexpected __riscv_xlen" -#endif - pmpaddr_csr = CSR_PMPADDR0 + n; + pmp.cfg = 0; - cfgmask = (0xffUL << pmpcfg_shift); - pmp.cfg = (csr_read_num(pmpcfg_csr) & cfgmask) >> pmpcfg_shift; - pmp.addr = csr_read_num(pmpaddr_csr); + return hart_pmp_write(&pmp, n); +} + +int is_pmp_entry_mapped(unsigned long entry) +{ + pmp_t pmp; + + if (hart_pmp_read(&pmp, entry) != SBI_OK) + return false; + + /* If address matching bits are non-zero, the entry is enable */ + if (pmp.cfg & PMP_A) + return true; + + return false; +} + +int pmp_set(unsigned int n, unsigned long prot, unsigned long addr, + unsigned long log2len) +{ + pmp_t pmp; + int rc; + + rc = pmp_encode(&pmp, prot, addr, log2len); + if (rc) + return rc; + + return hart_pmp_write(&pmp, n); +} + +int pmp_get(unsigned int n, unsigned long *prot_out, unsigned long *addr_out, + unsigned long *log2len) +{ + pmp_t pmp; + int rc; + + rc = hart_pmp_read(&pmp, n); + if (rc) + return rc; return pmp_decode(&pmp, prot_out, addr_out, log2len); } -- 2.53.0 -- opensbi mailing list opensbi@lists.infradead.org http://lists.infradead.org/mailman/listinfo/opensbi