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Wed, 29 Apr 2026 21:56:15 -0700 (PDT) Received: from localhost ([124.158.97.178]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2b98893f0b7sm42259725ad.40.2026.04.29.21.56.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Apr 2026 21:56:14 -0700 (PDT) From: Nicholas Piggin To: opensbi@lists.infradead.org Cc: Nicholas Piggin Subject: [PATCH 7/7] lib: sbi: Move hart PMP functions to sbi_hart_pmp.c Date: Thu, 30 Apr 2026 14:55:25 +1000 Message-ID: <20260430045528.420437-9-npiggin@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260430045528.420437-1-npiggin@gmail.com> References: <20260430045528.420437-1-npiggin@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260430_055618_412770_A169EEE6 X-CRM114-Status: GOOD ( 14.77 ) X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "opensbi" Errors-To: opensbi-bounces+opensbi=archiver.kernel.org@lists.infradead.org The sbi_hart_pmp.c looks like a good place for the hart PMP CSR access functions. Signed-off-by: Nicholas Piggin --- include/sbi/riscv_asm.h | 14 ----- include/sbi/sbi_hart_pmp.h | 12 ++++ lib/sbi/riscv_asm.c | 109 ------------------------------------ lib/sbi/sbi_hart_pmp.c | 110 +++++++++++++++++++++++++++++++++++++ 4 files changed, 122 insertions(+), 123 deletions(-) diff --git a/include/sbi/riscv_asm.h b/include/sbi/riscv_asm.h index f845320b..7765edb7 100644 --- a/include/sbi/riscv_asm.h +++ b/include/sbi/riscv_asm.h @@ -81,8 +81,6 @@ #ifndef __ASSEMBLER__ -#include - #define csr_swap(csr, val) \ ({ \ register unsigned long __v = (unsigned long)(val); \ @@ -211,18 +209,6 @@ int misa_xlen(void); /* Get RISC-V ISA string representation */ void misa_string(int xlen, char *out, unsigned int out_sz); -/* Disable pmp entry at a given index */ -int hart_pmp_disable(unsigned int n); - -/* Check if the matching field is set */ -bool hart_is_pmp_enabled(unsigned int n); - -int hart_pmp_set(unsigned int n, unsigned long prot, unsigned long addr, - unsigned long log2len); - -int hart_pmp_get(unsigned int n, unsigned long *prot_out, unsigned long *addr_out, - unsigned long *log2len); - #endif /* !__ASSEMBLER__ */ #endif diff --git a/include/sbi/sbi_hart_pmp.h b/include/sbi/sbi_hart_pmp.h index a7765d17..3e0219ac 100644 --- a/include/sbi/sbi_hart_pmp.h +++ b/include/sbi/sbi_hart_pmp.h @@ -9,6 +9,18 @@ #include +/* Disable pmp entry at a given index */ +int hart_pmp_disable(unsigned int n); + +/* Check if the matching field is set */ +bool hart_is_pmp_enabled(unsigned int n); + +int hart_pmp_set(unsigned int n, unsigned long prot, + unsigned long addr, unsigned long log2len); + +int hart_pmp_get(unsigned int n, unsigned long *prot_out, + unsigned long *addr_out, unsigned long *log2len); + struct sbi_scratch; unsigned int sbi_hart_pmp_count(struct sbi_scratch *scratch); diff --git a/lib/sbi/riscv_asm.c b/lib/sbi/riscv_asm.c index 98a93462..a1e0f2f8 100644 --- a/lib/sbi/riscv_asm.c +++ b/lib/sbi/riscv_asm.c @@ -272,112 +272,3 @@ void csr_write_num(int csr_num, unsigned long val) #undef switchcase_csr_write_2 #undef switchcase_csr_write } - -static int hart_pmp_read(pmp_t *pmp, unsigned int n) -{ - int pmpcfg_csr, pmpcfg_shift, pmpaddr_csr; - unsigned long cfgmask; - - /* check parameters */ - if (n >= PMP_COUNT) - return SBI_EINVAL; - - /* calculate PMP register and offset */ -#if __riscv_xlen == 32 - pmpcfg_csr = CSR_PMPCFG0 + (n >> 2); - pmpcfg_shift = (n & 3) << 3; -#elif __riscv_xlen == 64 - pmpcfg_csr = (CSR_PMPCFG0 + (n >> 2)) & ~1; - pmpcfg_shift = (n & 7) << 3; -#else -# error "Unexpected __riscv_xlen" -#endif - pmpaddr_csr = CSR_PMPADDR0 + n; - - cfgmask = (0xffUL << pmpcfg_shift); - pmp->cfg = (csr_read_num(pmpcfg_csr) & cfgmask) >> pmpcfg_shift; - pmp->addr = csr_read_num(pmpaddr_csr); - - return SBI_OK; -} - -static int hart_pmp_write(pmp_t *pmp, unsigned int n) -{ - int pmpcfg_csr, pmpcfg_shift, pmpaddr_csr; - unsigned long cfgmask, pmpcfg; - - /* check parameters */ - if (n >= PMP_COUNT) - return SBI_EINVAL; - - /* calculate PMP register and offset */ -#if __riscv_xlen == 32 - pmpcfg_csr = CSR_PMPCFG0 + (n >> 2); - pmpcfg_shift = (n & 3) << 3; -#elif __riscv_xlen == 64 - pmpcfg_csr = (CSR_PMPCFG0 + (n >> 2)) & ~1; - pmpcfg_shift = (n & 7) << 3; -#else -# error "Unexpected __riscv_xlen" -#endif - pmpaddr_csr = CSR_PMPADDR0 + n; - - /* write csrs */ - csr_write_num(pmpaddr_csr, pmp->addr); - cfgmask = ~(0xffUL << pmpcfg_shift); - pmpcfg = (csr_read_num(pmpcfg_csr) & cfgmask); - pmpcfg |= (((unsigned long)pmp->cfg << pmpcfg_shift) & ~cfgmask); - csr_write_num(pmpcfg_csr, pmpcfg); - - return SBI_OK; -} - -int hart_pmp_disable(unsigned int n) -{ - pmp_t pmp; - int rc; - - rc = hart_pmp_read(&pmp, n); - if (rc) - return rc; - - pmp.cfg = 0; - - return hart_pmp_write(&pmp, n); -} - -bool hart_is_pmp_enabled(unsigned int n) -{ - pmp_t pmp; - - if (hart_pmp_read(&pmp, n) != SBI_OK) - return false; - - return pmp_is_enabled(&pmp); -} - -int hart_pmp_set(unsigned int n, unsigned long prot, unsigned long addr, - unsigned long log2len) -{ - pmp_t pmp; - int rc; - - rc = pmp_encode(&pmp, prot, addr, log2len); - if (rc) - return rc; - - return hart_pmp_write(&pmp, n); -} - -int hart_pmp_get(unsigned int n, unsigned long *prot_out, unsigned long *addr_out, - unsigned long *log2len) -{ - pmp_t pmp; - int rc; - - rc = hart_pmp_read(&pmp, n); - if (rc) - return rc; - - return pmp_decode(&pmp, prot_out, addr_out, log2len); -} diff --git a/lib/sbi/sbi_hart_pmp.c b/lib/sbi/sbi_hart_pmp.c index 8b7b091c..54cfd0cb 100644 --- a/lib/sbi/sbi_hart_pmp.c +++ b/lib/sbi/sbi_hart_pmp.c @@ -12,9 +12,119 @@ #include #include #include +#include #include #include +static int hart_pmp_read(pmp_t *pmp, unsigned int n) +{ + int pmpcfg_csr, pmpcfg_shift, pmpaddr_csr; + unsigned long cfgmask; + + /* check parameters */ + if (n >= PMP_COUNT) + return SBI_EINVAL; + + /* calculate PMP register and offset */ +#if __riscv_xlen == 32 + pmpcfg_csr = CSR_PMPCFG0 + (n >> 2); + pmpcfg_shift = (n & 3) << 3; +#elif __riscv_xlen == 64 + pmpcfg_csr = (CSR_PMPCFG0 + (n >> 2)) & ~1; + pmpcfg_shift = (n & 7) << 3; +#else +# error "Unexpected __riscv_xlen" +#endif + pmpaddr_csr = CSR_PMPADDR0 + n; + + cfgmask = (0xffUL << pmpcfg_shift); + pmp->cfg = (csr_read_num(pmpcfg_csr) & cfgmask) >> pmpcfg_shift; + pmp->addr = csr_read_num(pmpaddr_csr); + + return SBI_OK; +} + +static int hart_pmp_write(pmp_t *pmp, unsigned int n) +{ + int pmpcfg_csr, pmpcfg_shift, pmpaddr_csr; + unsigned long cfgmask, pmpcfg; + + /* check parameters */ + if (n >= PMP_COUNT) + return SBI_EINVAL; + + /* calculate PMP register and offset */ +#if __riscv_xlen == 32 + pmpcfg_csr = CSR_PMPCFG0 + (n >> 2); + pmpcfg_shift = (n & 3) << 3; +#elif __riscv_xlen == 64 + pmpcfg_csr = (CSR_PMPCFG0 + (n >> 2)) & ~1; + pmpcfg_shift = (n & 7) << 3; +#else +# error "Unexpected __riscv_xlen" +#endif + pmpaddr_csr = CSR_PMPADDR0 + n; + + /* write csrs */ + csr_write_num(pmpaddr_csr, pmp->addr); + cfgmask = ~(0xffUL << pmpcfg_shift); + pmpcfg = (csr_read_num(pmpcfg_csr) & cfgmask); + pmpcfg |= (((unsigned long)pmp->cfg << pmpcfg_shift) & ~cfgmask); + csr_write_num(pmpcfg_csr, pmpcfg); + + return SBI_OK; +} + +int hart_pmp_disable(unsigned int n) +{ + pmp_t pmp; + int rc; + + rc = hart_pmp_read(&pmp, n); + if (rc) + return rc; + + pmp.cfg = 0; + + return hart_pmp_write(&pmp, n); +} + +bool hart_is_pmp_enabled(unsigned int n) +{ + pmp_t pmp; + + if (hart_pmp_read(&pmp, n) != SBI_OK) + return false; + + return pmp_is_enabled(&pmp); +} + +int hart_pmp_set(unsigned int n, unsigned long prot, unsigned long addr, + unsigned long log2len) +{ + pmp_t pmp; + int rc; + + rc = pmp_encode(&pmp, prot, addr, log2len); + if (rc) + return rc; + + return hart_pmp_write(&pmp, n); +} + +int hart_pmp_get(unsigned int n, unsigned long *prot_out, unsigned long *addr_out, + unsigned long *log2len) +{ + pmp_t pmp; + int rc; + + rc = hart_pmp_read(&pmp, n); + if (rc) + return rc; + + return pmp_decode(&pmp, prot_out, addr_out, log2len); +} + /* * Smepmp enforces access boundaries between M-mode and * S/U-mode. When it is enabled, the PMPs are programmed -- 2.53.0 -- opensbi mailing list opensbi@lists.infradead.org http://lists.infradead.org/mailman/listinfo/opensbi