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Fri, 26 Jun 2026 03:16:39 -0700 (PDT) Received: from hsinchu16.internal.sifive.com ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-845a3ec0ec9sm6414226b3a.0.2026.06.26.03.16.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jun 2026 03:16:38 -0700 (PDT) From: Yu-Chien Peter Lin To: opensbi@lists.infradead.org Cc: zong.li@sifive.com, greentime.hu@sifive.com, anup@brainfault.org, scott@riscstar.com, conor@kernel.org, dave.patel@riscstar.com, raymond.mao@riscstar.com, robin.randhawa@sifive.com, samuel.holland@sifive.com, Yu-Chien Peter Lin Subject: [RFC PATCH 02/12] lib: utils: fdt_helper: parse RISC-V Worlds DT properties Date: Fri, 26 Jun 2026 18:14:23 +0800 Message-ID: <20260626101433.3133466-3-peter.lin@sifive.com> X-Mailer: git-send-email 2.48.0 In-Reply-To: <20260626101433.3133466-1-peter.lin@sifive.com> References: <20260626101433.3133466-1-peter.lin@sifive.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260626_031640_422855_06FF09E2 X-CRM114-Status: GOOD ( 15.48 ) X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "opensbi" Errors-To: opensbi-bounces+opensbi=archiver.kernel.org@lists.infradead.org Add fdt_parse_worlds_all_harts() to parse RISC-V Worlds device tree properties from CPU nodes: - riscv,pmwid (u32): Physical Machine World ID for this hart - riscv,pmwidlist (u64): Bitmap of permitted M-mode World IDs - riscv,pmlwidlist (u64): Bitmap of permitted S/U-mode World IDs This patch extends the sbi_hart_features struct with new fields to store the parsed World ID configuration (has_pmwid, pmwid, pmwidlist, and pmlwidlist). Link: https://lore.kernel.org/all/20260619105834.1277302-3-peter.lin@sifive.com/ Signed-off-by: Yu-Chien Peter Lin --- include/sbi/sbi_hart.h | 15 ++++++++ include/sbi_utils/fdt/fdt_helper.h | 2 + lib/utils/fdt/fdt_helper.c | 61 ++++++++++++++++++++++++++++++ platform/generic/platform.c | 13 ++++++- 4 files changed, 90 insertions(+), 1 deletion(-) diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h index 2941809e..97072c09 100644 --- a/include/sbi/sbi_hart.h +++ b/include/sbi/sbi_hart.h @@ -135,6 +135,21 @@ struct sbi_hart_features { unsigned int pmp_log2gran; unsigned int mhpm_mask; unsigned int mhpm_bits; + /** True if riscv,pmwid was present in DT */ + bool has_pmwid; + u32 pmwid; + /** + * Platform-defined bitmap of M-mode WIDs + * (from DT riscv,pmwidlist). Zero means + * absent/unrestricted. + */ + u64 pmwidlist; + /** + * Platform-defined bitmap of S/U-mode WIDs + * (from DT riscv,pmlwidlist). Zero means + * absent/unrestricted. + */ + u64 pmlwidlist; }; extern unsigned long hart_features_offset; diff --git a/include/sbi_utils/fdt/fdt_helper.h b/include/sbi_utils/fdt/fdt_helper.h index 75a564d1..3f3d091b 100644 --- a/include/sbi_utils/fdt/fdt_helper.h +++ b/include/sbi_utils/fdt/fdt_helper.h @@ -56,6 +56,8 @@ int fdt_parse_timebase_frequency(const void *fdt, unsigned long *freq); int fdt_parse_isa_extensions_all_harts(const void *fdt); +int fdt_parse_worlds_all_harts(const void *fdt); + int fdt_parse_gaisler_uart_node(const void *fdt, int nodeoffset, struct platform_uart_data *uart); diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c index ad4efaaf..8b40cd28 100644 --- a/lib/utils/fdt/fdt_helper.c +++ b/lib/utils/fdt/fdt_helper.c @@ -457,6 +457,67 @@ int fdt_parse_isa_extensions_all_harts(const void *fdt) return 0; } +int fdt_parse_worlds_all_harts(const void *fdt) +{ + u32 hartid; + const fdt32_t *val; + struct sbi_scratch *scratch; + struct sbi_hart_features *hfeatures; + int err, cpu_offset, cpus_offset, len; + + if (!fdt) + return SBI_EINVAL; + + cpus_offset = fdt_path_offset(fdt, "/cpus"); + if (cpus_offset < 0) + return cpus_offset; + + fdt_for_each_subnode(cpu_offset, fdt, cpus_offset) { + err = fdt_parse_hart_id(fdt, cpu_offset, &hartid); + if (err) + continue; + + if (!fdt_node_is_enabled(fdt, cpu_offset)) + continue; + + scratch = sbi_hartid_to_scratch(hartid); + if (!scratch) + return SBI_ENOENT; + + hfeatures = sbi_hart_features_ptr(scratch); + if (!hfeatures) + return SBI_ENOENT; + + val = fdt_getprop(fdt, cpu_offset, "riscv,pmwid", &len); + if (val && len == sizeof(fdt32_t)) { + hfeatures->pmwid = fdt32_to_cpu(*val); + hfeatures->has_pmwid = true; + } + + val = fdt_getprop(fdt, cpu_offset, "riscv,pmwidlist", &len); + if (val && len == 2 * sizeof(fdt32_t)) { + hfeatures->pmwidlist = ((u64)fdt32_to_cpu(val[0]) << 32) | + fdt32_to_cpu(val[1]); + } + + val = fdt_getprop(fdt, cpu_offset, "riscv,pmlwidlist", &len); + if (val && len == 2 * sizeof(fdt32_t)) { + hfeatures->pmlwidlist = ((u64)fdt32_to_cpu(val[0]) << 32) | + fdt32_to_cpu(val[1]); + } + + /* Sanity checks */ + if (hfeatures->has_pmwid && (hfeatures->pmwid >= 64)) + return SBI_EINVAL; + if (hfeatures->has_pmwid && hfeatures->pmwidlist && + !(hfeatures->pmwidlist & BIT_ULL(hfeatures->pmwid))) { + return SBI_EINVAL; + } + } + + return 0; +} + static int fdt_parse_uart_node_common(const void *fdt, int nodeoffset, struct platform_uart_data *uart, unsigned long default_freq, diff --git a/platform/generic/platform.c b/platform/generic/platform.c index 1df0280d..51e9f342 100644 --- a/platform/generic/platform.c +++ b/platform/generic/platform.c @@ -255,11 +255,22 @@ int generic_final_init(bool cold_boot) int generic_extensions_init(bool cold_boot) { + int rc; + if (!cold_boot) return 0; /* Parse the ISA string from FDT and enable the listed extensions */ - return fdt_parse_isa_extensions_all_harts(fdt_get_address()); + rc = fdt_parse_isa_extensions_all_harts(fdt_get_address()); + if (rc) + return rc; + + /* Parse RISC-V Worlds CPU properties from FDT */ + rc = fdt_parse_worlds_all_harts(fdt_get_address()); + if (rc) + return rc; + + return 0; } int generic_domains_init(void) -- 2.43.7 -- opensbi mailing list opensbi@lists.infradead.org http://lists.infradead.org/mailman/listinfo/opensbi