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From: Ben Zong-You Xie <ben717@andestech.com>
To: <opensbi@lists.infradead.org>
Subject: [PATCH 5/7] lib: utils/hsm: wake sleeping Andes harts with an IPI
Date: Tue, 28 Jul 2026 16:10:39 +0800	[thread overview]
Message-ID: <20260728081041.2724668-6-ben717@andestech.com> (raw)
In-Reply-To: <20260728081041.2724668-1-ben717@andestech.com>

An IPI wakes a hart from light sleep and, once MSIP is kept as an SMU
wakeup event, from deep sleep too. Drop the WAKEUP_CMD path and the boot
state, hart type and sleep type conditions that selected it.

Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
---
 include/sbi_utils/hsm/fdt_hsm_andes_atcsmu.h |  1 +
 lib/utils/hsm/fdt_hsm_andes_atcsmu.c         | 21 +++++---------------
 lib/utils/suspend/fdt_suspend_andes_atcsmu.c |  8 +++-----
 3 files changed, 9 insertions(+), 21 deletions(-)

diff --git a/include/sbi_utils/hsm/fdt_hsm_andes_atcsmu.h b/include/sbi_utils/hsm/fdt_hsm_andes_atcsmu.h
index 5e71fab7c69e..20e6cea09379 100644
--- a/include/sbi_utils/hsm/fdt_hsm_andes_atcsmu.h
+++ b/include/sbi_utils/hsm/fdt_hsm_andes_atcsmu.h
@@ -36,6 +36,7 @@
 #define PCS_WAKEUP_RTC_ALARM_MASK	BIT(2)
 #define PCS_WAKEUP_UART2_MASK		BIT(9)
 #define PCS_WAKEUP_MSIP_MASK		BIT(29)
+#define PCS_WAKEUP_MEIP_MASK		BIT(31)
 
 #define PCS0_CTL_OFFSET			0x94
 #define PCSm_CTL_OFFSET(i)		((i + 3) * 0x20 + PCS0_CTL_OFFSET)
diff --git a/lib/utils/hsm/fdt_hsm_andes_atcsmu.c b/lib/utils/hsm/fdt_hsm_andes_atcsmu.c
index ae1d88892f14..dfbb425cd2ad 100644
--- a/lib/utils/hsm/fdt_hsm_andes_atcsmu.c
+++ b/lib/utils/hsm/fdt_hsm_andes_atcsmu.c
@@ -116,20 +116,8 @@ bool atcsmu_pcs_is_sleep(u32 hartid, bool deep_sleep)
 static int ae350_hart_start(u32 hartid, ulong saddr)
 {
 	u32 hartindex = sbi_hartid_to_hartindex(hartid);
-	u32 sleep_type = atcsmu_get_sleep_type(hartid);
 
-	/*
-	 * Don't send wakeup command when:
-	 * 1) boot time
-	 * 2) the target hart is non-sleepable 25-series hart0
-	 * 3) light sleep
-	 */
-	if (!sbi_init_count(hartindex) || (is_andes(25) && hartid == 0) ||
-	    sleep_type == SBI_SUSP_AE350_LIGHT_SLEEP)
-		return sbi_ipi_raw_send(hartindex, false);
-
-	atcsmu_set_command(WAKEUP_CMD, hartid);
-	return 0;
+	return sbi_ipi_raw_send(hartindex, false);
 }
 
 static int ae350_hart_stop(void)
@@ -152,12 +140,13 @@ static int ae350_hart_stop(void)
 	/* Prevent the core leaving the WFI mode unexpectedly */
 	csr_write(CSR_MIE, 0);
 
+	atcsmu_set_wakeup_events(PCS_WAKEUP_MSIP_MASK | PCS_WAKEUP_MEIP_MASK, hartid);
 	if (sleep_type == SBI_SUSP_AE350_LIGHT_SLEEP) {
-		csr_write(CSR_MIE, MIP_MSIP);
-		atcsmu_set_wakeup_events(PCS_WAKEUP_MSIP_MASK, hartid);
+		/* Clock-gated only: needs MSI or MEI set to resume past the WFI */
+		csr_set(CSR_MIE, MIP_MSIP | MIP_MEIP);
 		atcsmu_set_command(LIGHT_SLEEP_CMD, hartid);
 	} else if (sleep_type == SBI_SUSP_SLEEP_TYPE_SUSPEND) {
-		atcsmu_set_wakeup_events(0x0, hartid);
+		/* Power-gated: SMU wakes it via cold reset, interrupts not needed */
 		atcsmu_set_command(DEEP_SLEEP_CMD, hartid);
 		rc = atcsmu_set_reset_vector((ulong)ae350_enable_coherency_warmboot, hartid);
 		if (rc)
diff --git a/lib/utils/suspend/fdt_suspend_andes_atcsmu.c b/lib/utils/suspend/fdt_suspend_andes_atcsmu.c
index 6722b70f0e6e..ced0eb41d5b7 100644
--- a/lib/utils/suspend/fdt_suspend_andes_atcsmu.c
+++ b/lib/utils/suspend/fdt_suspend_andes_atcsmu.c
@@ -47,11 +47,7 @@ static int ae350_system_suspend(u32 sleep_type, unsigned long addr)
 	/* Prevent the core leaving the WFI mode unexpectedly */
 	csr_write(CSR_MIE, 0);
 
-	/*
-	 * Only allow the S-mode external interrupts (UART2 and RTC alarm) to
-	 * wake up the primary hart
-	 */
-	csr_set(CSR_SIE, MIP_SEIP);
+	/* SMU wakes the primary hart on RTC alarm / UART2 */
 	atcsmu_set_wakeup_events(PCS_WAKEUP_RTC_ALARM_MASK | PCS_WAKEUP_UART2_MASK, hartid);
 
 	if (sleep_type == SBI_SUSP_AE350_LIGHT_SLEEP) {
@@ -59,6 +55,8 @@ static int ae350_system_suspend(u32 sleep_type, unsigned long addr)
 		if (rc)
 			return rc;
 
+		/* Clock-gated only: enable SEI to resume past the WFI */
+		csr_set(CSR_MIE, MIP_SEIP);
 		atcsmu_set_command(LIGHT_SLEEP_CMD, hartid);
 	} else if (sleep_type == SBI_SUSP_SLEEP_TYPE_SUSPEND) {
 		rc = check_secondary_harts_sleep(hartid, true);
-- 
2.34.1


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  parent reply	other threads:[~2026-07-28  8:11 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-28  8:10 [PATCH 0/7] Fix and improve the Andes ATCSMU and LLC drivers Ben Zong-You Xie
2026-07-28  8:10 ` [PATCH 1/7] lib: utils/cache: fix andes_llcache_enable() return value Ben Zong-You Xie
2026-07-28  8:10 ` [PATCH 2/7] lib: utils/andes: add the SMU and LLC registers to the root domain Ben Zong-You Xie
2026-07-28  8:10 ` [PATCH 3/7] platform: generic/andes: pair non-retentive CSR save/restore with a flag Ben Zong-You Xie
2026-07-28  8:10 ` [PATCH 4/7] lib: utils/suspend: restore Andes CSRs on system-suspend resume Ben Zong-You Xie
2026-07-28  8:10 ` Ben Zong-You Xie [this message]
2026-07-28  8:10 ` [PATCH 6/7] lib: utils/suspend: wait for the secondary Andes harts to sleep Ben Zong-You Xie
2026-07-28  8:10 ` [PATCH 7/7] lib: utils/andes: arm the SMU sleep command last Ben Zong-You Xie

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