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Thu, 20 Aug 2026 01:40:18 -0700 (PDT) Received: from [192.168.0.13] ([172.92.174.155]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2d62e3affeesm3746845ad.65.2026.08.20.01.40.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 20 Aug 2026 01:40:17 -0700 (PDT) Message-ID: <2ab3f4f0-a3fc-41ea-ae1f-640871e76c8c@gmail.com> Date: Thu, 20 Aug 2026 01:40:10 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/5] lib: sbi: select expected trap handler per hart To: Troy Mitchell , opensbi@lists.infradead.org Cc: Xianbin Zhu , Anup Patel , Bo Gan References: <20260818-spacemit-k3-v2-0-84cb7773a481@linux.spacemit.com> <20260818-spacemit-k3-v2-1-84cb7773a481@linux.spacemit.com> Content-Language: en-US From: Bo Gan In-Reply-To: <20260818-spacemit-k3-v2-1-84cb7773a481@linux.spacemit.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260820_014019_932484_295ABFBF X-CRM114-Status: GOOD ( 17.58 ) X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "opensbi" Errors-To: opensbi-bounces+opensbi=archiver.kernel.org@lists.infradead.org On 8/17/26 18:14, Troy Mitchell wrote: > The expected trap handler is selected once by the cold boot hart. This > breaks heterogeneous systems where the cold boot hart implements H but > another hart does not, because the H-aware handler accesses mtval2 and > mtinst. > > Select the handler from the current hart's MISA at each use so every > hart uses only the CSRs it implements. > > Fixes: 1de66d170e71 ("lib: Optimize unpriv load/store implementation") > Reported-by: Bo Gan > Link: https://lore.kernel.org/r/e702f291-dde8-4b99-a65e-182d2b847720@gmail.com > Suggested-by: Bo Gan > Signed-off-by: Troy Mitchell Reading PATCH 5/5, I realized H can be dynamically turned on/off for X100, so dynamically determine expected_trap_addr makes even more sense now. Reviewed-by: Bo Gan Bo > --- > include/sbi/sbi_csr_detect.h | 4 ++-- > include/sbi/sbi_hart.h | 2 +- > lib/sbi/sbi_hart.c | 9 +++++---- > lib/sbi/sbi_illegal_atomic.c | 4 ++-- > lib/sbi/sbi_unpriv.c | 6 +++--- > 5 files changed, 13 insertions(+), 12 deletions(-) > > diff --git a/include/sbi/sbi_csr_detect.h b/include/sbi/sbi_csr_detect.h > index 097c31c8..31e50db9 100644 > --- a/include/sbi/sbi_csr_detect.h > +++ b/include/sbi/sbi_csr_detect.h > @@ -16,9 +16,9 @@ > > #define csr_read_allowed(csr_num, trap) \ > ({ \ > + register ulong mtvec = sbi_hart_expected_trap_addr(); \ > register ulong tinfo asm("a3") = (ulong)trap; \ > register ulong ttmp asm("a4"); \ > - register ulong mtvec = (ulong)sbi_hart_expected_trap; \ > register ulong ret = 0; \ > ((struct sbi_trap_info *)(trap))->cause = 0; \ > asm volatile( \ > @@ -35,9 +35,9 @@ > > #define csr_write_allowed(csr_num, trap, value) \ > ({ \ > + register ulong mtvec = sbi_hart_expected_trap_addr(); \ > register ulong tinfo asm("a3") = (ulong)trap; \ > register ulong ttmp asm("a4"); \ > - register ulong mtvec = (ulong)sbi_hart_expected_trap; \ > ((struct sbi_trap_info *)(trap))->cause = 0; \ > asm volatile( \ > "add %[ttmp], %[tinfo], zero\n" \ > diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h > index 543393bb..6f4ee31e 100644 > --- a/include/sbi/sbi_hart.h > +++ b/include/sbi/sbi_hart.h > @@ -135,7 +135,7 @@ struct sbi_scratch; > int sbi_hart_reinit(struct sbi_scratch *scratch); > int sbi_hart_init(struct sbi_scratch *scratch, bool cold_boot); > > -extern void (*sbi_hart_expected_trap)(void); > +ulong sbi_hart_expected_trap_addr(void); > > unsigned int sbi_hart_mhpm_mask(struct sbi_scratch *scratch); > void sbi_hart_delegation_dump(struct sbi_scratch *scratch, > diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c > index bee88557..14e44955 100644 > --- a/lib/sbi/sbi_hart.c > +++ b/lib/sbi/sbi_hart.c > @@ -25,7 +25,11 @@ > extern void __sbi_expected_trap(void); > extern void __sbi_expected_trap_hext(void); > > -void (*sbi_hart_expected_trap)(void) = &__sbi_expected_trap; > +ulong sbi_hart_expected_trap_addr(void) > +{ > + return misa_extension('H') ? (ulong)&__sbi_expected_trap_hext : > + (ulong)&__sbi_expected_trap; > +} > > unsigned long hart_features_offset; > > @@ -712,9 +716,6 @@ int sbi_hart_init(struct sbi_scratch *scratch, bool cold_boot) > csr_write(CSR_MIP, 0); > > if (cold_boot) { > - if (misa_extension('H')) > - sbi_hart_expected_trap = &__sbi_expected_trap_hext; > - > hart_features_offset = sbi_scratch_alloc_offset( > sizeof(struct sbi_hart_features)); > if (!hart_features_offset) > diff --git a/lib/sbi/sbi_illegal_atomic.c b/lib/sbi/sbi_illegal_atomic.c > index 977a9ad0..30f5118e 100644 > --- a/lib/sbi/sbi_illegal_atomic.c > +++ b/lib/sbi/sbi_illegal_atomic.c > @@ -30,7 +30,7 @@ int sbi_illegal_atomic(ulong insn, struct sbi_trap_regs *regs) > { \ > register ulong tinfo asm("a3"); \ > register ulong mstatus = 0; \ > - register ulong mtvec = (ulong)sbi_hart_expected_trap; \ > + register ulong mtvec = sbi_hart_expected_trap_addr(); \ > type ret = 0; \ > trap->cause = 0; \ > asm volatile( \ > @@ -57,7 +57,7 @@ int sbi_illegal_atomic(ulong insn, struct sbi_trap_regs *regs) > { \ > register ulong tinfo asm("a3"); \ > register ulong mstatus = 0; \ > - register ulong mtvec = (ulong)sbi_hart_expected_trap; \ > + register ulong mtvec = sbi_hart_expected_trap_addr(); \ > type ret = 0; \ > trap->cause = 0; \ > asm volatile( \ > diff --git a/lib/sbi/sbi_unpriv.c b/lib/sbi/sbi_unpriv.c > index 60becedc..1550d111 100644 > --- a/lib/sbi/sbi_unpriv.c > +++ b/lib/sbi/sbi_unpriv.c > @@ -33,9 +33,9 @@ union sbi_unpriv_data { > type sbi_load_##type(const type *addr, \ > struct sbi_trap_info *trap) \ > { \ > + register ulong mtvec = sbi_hart_expected_trap_addr(); \ > register ulong tinfo asm("a3") = (ulong)trap; \ > register ulong mstatus = 0; \ > - register ulong mtvec = (ulong)sbi_hart_expected_trap; \ > type ret = 0; \ > trap->cause = 0; \ > asm volatile( \ > @@ -58,9 +58,9 @@ union sbi_unpriv_data { > void sbi_store_##type(type *addr, type val, \ > struct sbi_trap_info *trap) \ > { \ > + register ulong mtvec = sbi_hart_expected_trap_addr(); \ > register ulong tinfo asm("a3") = (ulong)trap; \ > register ulong mstatus = 0; \ > - register ulong mtvec = (ulong)sbi_hart_expected_trap; \ > trap->cause = 0; \ > asm volatile( \ > "csrrw %[mtvec], " STR(CSR_MTVEC) ", %[mtvec]\n" \ > @@ -207,7 +207,7 @@ ulong sbi_get_insn(ulong mepc, struct sbi_trap_info *trap) > register ulong tinfo asm("a3"); > register ulong ttmp asm("a4"); > register ulong mstatus = 0; > - register ulong mtvec = (ulong)sbi_hart_expected_trap; > + register ulong mtvec = sbi_hart_expected_trap_addr(); > ulong insn = 0; > > trap->cause = 0; > -- opensbi mailing list opensbi@lists.infradead.org http://lists.infradead.org/mailman/listinfo/opensbi