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From: "Radim Krčmář" <rkrcmar@ventanamicro.com>
To: "Deepak Gupta" <debug@rivosinc.com>
Cc: <opensbi@lists.infradead.org>,
	"opensbi" <opensbi-bounces@lists.infradead.org>
Subject: Re: [PATCH] lib: sbi: expected trap must always clear MPRV
Date: Wed, 26 Nov 2025 09:21:16 +0100	[thread overview]
Message-ID: <DEIHB3SVYL4W.119RRX5IAT3A5@ventanamicro.com> (raw)
In-Reply-To: <aSYL3FUKAKfyDgqY@debug.ba.rivosinc.com>

2025-11-25T12:04:44-08:00, Deepak Gupta <debug@rivosinc.com>:
> On Tue, Nov 25, 2025 at 08:48:35PM +0100, Radim Krčmář wrote:
>>2025-11-25T11:17:29-08:00, Deepak Gupta <debug@rivosinc.com>:
>>> I can modify the commit message to remove security impact (that it seems like
>>> how implementations are implementing it) and re-send it.
>>
>>That would help.  The patch also uses a wrong bitmask for csrc:
>>MPRV is bit 17, but you're clearing bit 5, SPIE.
>>(Isn't it possible to use MSTATUS_MPRV there?)
>
> It's `lui` (load upper immediate). I could just do `li a4, MTSTATUS_PRV`.
> Although its a larger immediate, so most likely assembler will split into
> two instructions or would replace it with `lui`.

Sorry, I missed that.  Yeah, assembler should translate it to just lui.

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  reply	other threads:[~2025-11-26  8:21 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-24 22:03 [PATCH] lib: sbi: expected trap must always clear MPRV Deepak Gupta
2025-11-25 11:12 ` Radim Krčmář
2025-11-25 18:03   ` Deepak Gupta
2025-11-25 18:51     ` Radim Krčmář
2025-11-25 19:17       ` Deepak Gupta
2025-11-25 19:48         ` Radim Krčmář
2025-11-25 20:04           ` Deepak Gupta
2025-11-26  8:21             ` Radim Krčmář [this message]
2025-12-26 11:06 ` Anup Patel

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