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[86.49.253.11]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43569921dedsm22634940f8f.9.2026.01.19.03.57.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jan 2026 03:57:17 -0800 (PST) Mime-Version: 1.0 Date: Mon, 19 Jan 2026 11:57:16 +0000 Message-Id: Subject: Re: [PATCH] lib: sbi_pmu: Add FW counter index validation when reading high bits on RV64 Cc: , , "opensbi" To: "James Raphael Tiovalen" , From: =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= References: <20260117125031.56031-1-jamestiotio@gmail.com> In-Reply-To: <20260117125031.56031-1-jamestiotio@gmail.com> X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTE5MDA5OSBTYWx0ZWRfX8wgwsGEbn/t3 NUC/wVcTY/IQyfQk/NQRlviWylPGrG73NX/jA8d8K9VmGaNJIDfLhGpNPkFYQ448SFvEMx8taSg voLCr+ClXcAgkImu5vpbqVcmR8VXHTWcIQJ2ufFFznYUYrsiu5NNDrQdoKR1PnZllNPdxNLsM1I S79wxw5U0g17ZbPPpin6i4TiPJ42IQJBYFjjxHEMtkeC3NZ5kJdwHddNjxKkBISPulEvxHg2pUc BeavDuiGCbss8khnAQpt1M2GFZ1CLLIMGeKL72iGQ1hW5ww2Ih/TeTT5uqRdsfyzmVhGbocvOAJ YzKar0o5nDYjwCqoYYW5rdFNS0zczeHFB5LGr2uPtcfhYtNoxWp/tVNqh3F7gqq1bIRLsfDAtWF p3c+P/f9Oduv4PbdIkcZ9sAsAytJay0E3qOeaiSCJROOmVLM/+AJOY8lj/GsUzMEJYXO0EnSTQT /41JlbOeS2A1X0yB6ag== X-Proofpoint-ORIG-GUID: oKmSZZI8PvZOOR1hLuaTC-doG36wfrdZ X-Proofpoint-GUID: oKmSZZI8PvZOOR1hLuaTC-doG36wfrdZ X-Authority-Analysis: v=2.4 cv=L8gQguT8 c=1 sm=1 tr=0 ts=696e1c1f cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=HFCiZzTCIv7qJCpyeE1rag==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=pGLkceISAAAA:8 a=5zEJGDWQOOdwX-l-qeQA:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-19_02,2026-01-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 impostorscore=0 suspectscore=0 phishscore=0 spamscore=0 clxscore=1011 priorityscore=1501 lowpriorityscore=0 bulkscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601190099 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260119_035721_309881_D41A2256 X-CRM114-Status: GOOD ( 17.92 ) X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "opensbi" Errors-To: opensbi-bounces+opensbi=archiver.kernel.org@lists.infradead.org 2026-01-17T20:50:31+08:00, James Raphael Tiovalen : > Currently, when we attempt to read the upper 32 bits of a firmware > counter on RV64 or higher, we just set `sbiret.value` to 0 without > validating the counter index. The SBI specification requires us to set > `sbiret.error` to `SBI_ERR_INVALID_PARAM` if the counter index points to > a hardware counter or an invalid counter. Add a validation check to > ensure compliance with the specification on RV64 or higher. > > Fixes: 51951d9e9af8 ("lib: sbi_pmu: Implement sbi_pmu_counter_fw_read_hi") > Signed-off-by: James Raphael Tiovalen > --- While the call is poorly specified and your interpretation is valid, I think the intention is to make this function do nothing else than return {err, 0} on RV64 as there isn't much reason to complicate the implementation. I think always returning {SBI_EINVAL, 0} would be even better than the current {SBI_SUCCESS, 0}, but it doesn't matter much since legitimate RV64 software shouldn't ever invoke the ecall. > diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c > @@ -227,6 +227,14 @@ static bool pmu_ctr_idx_validate(unsigned long cbase, unsigned long cmask) > return cmask && cbase + sbi_fls(cmask) < total_ctrs; > } In case of disagreement with the above: > +int sbi_pmu_is_fw_ctr_idx(uint32_t cidx) > +{ This functions gets passed regs->a0, so cidx should be an xlen sized type. (I understand trying to be consistent, as sbi_pmu_ctr_fw_read has the same bug, but better fix related code when touching it.) > + if (cidx < num_hw_ctrs || cidx >= total_ctrs) > + return SBI_EINVAL; Please refactor the check in sbi_pmu_ctr_fw_read, and use it instead of adding more logic. Thanks. -- opensbi mailing list opensbi@lists.infradead.org http://lists.infradead.org/mailman/listinfo/opensbi