[PATCH v3 1/3] lib: sbi: Add RISC-V vector context save/restore support

[PATCH v3 1/3] lib: sbi: Add RISC-V vector context save/restore support

[dave.patel]

From: Dave Patel <dave.patel@riscstar.com>

Eager context switch: Add support for saving and restoring RISC-V vector
extension state in OpenSBI. This introduces a per-hart vector context
structure and helper routines to perform full context save and restore.

The vector context includes vl, vtype, vcsr CSRs along with storage for all
32 vector registers. The register state is saved and restored using byte-wise
vector load/store instructions (vse8.v/vle8.v), making the implementation
independent of current SEW/LMUL configuration.

The implementation follows an eager context switching model where the entire
vector state is saved and restored on every context switch. This provides a
simple and deterministic mechanism without requiring lazy trap-based
management.

Notes:
- The SBI_MAX_VLENB is configured using CONFIG_SBI_MAX_VLENB.

Signed-off-by: Dave Patel <dave.patel@riscstar.com>
---
 include/sbi/sbi_vector.h |  30 ++++++
 lib/sbi/Kconfig          |   4 +
 lib/sbi/objects.mk       |   1 +
 lib/sbi/sbi_vector.c     | 215 +++++++++++++++++++++++++++++++++++++++
 4 files changed, 250 insertions(+)
 create mode 100644 include/sbi/sbi_vector.h
 create mode 100644 lib/sbi/sbi_vector.c

diff --git a/include/sbi/sbi_vector.h b/include/sbi/sbi_vector.h
new file mode 100644
index 00000000..4ecfaa0b
--- /dev/null
+++ b/include/sbi/sbi_vector.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2026 RISCstar Solutions.
+ *
+ * Authors:
+ *   Dave Patel <dave.patel@riscstar.com>
+ */
+
+#ifndef __SBI_VECTOR_H__
+#define __SBI_VECTOR_H__
+
+#include <sbi/sbi_types.h>
+
+#define SBI_MAX_VLENB CONFIG_SBI_MAX_VLENB
+
+struct sbi_vector_context {
+	unsigned long vl;
+	unsigned long vtype;
+	unsigned long vcsr;
+	unsigned long vstart;
+
+	/* size depends on VLEN */
+	uint8_t vregs[32 * SBI_MAX_VLENB];
+};
+
+void sbi_vector_save(struct sbi_vector_context *dst);
+void sbi_vector_restore(const struct sbi_vector_context *src);
+
+#endif //__SBI_VECTOR_H__
+
diff --git a/lib/sbi/Kconfig b/lib/sbi/Kconfig
index 8479f861..b2432150 100644
--- a/lib/sbi/Kconfig
+++ b/lib/sbi/Kconfig
@@ -74,4 +74,8 @@ config SBI_ECALL_VIRQ
 	bool "VIRQ extension"
 	default y

+config SBI_MAX_VLENB
+	int "Vector VLENB size"
+	default 256
+
 endmenu
diff --git a/lib/sbi/objects.mk b/lib/sbi/objects.mk
index ea816e92..5c0caf39 100644
--- a/lib/sbi/objects.mk
+++ b/lib/sbi/objects.mk
@@ -106,3 +106,4 @@ libsbi-objs-y += sbi_trap_v_ldst.o
 libsbi-objs-y += sbi_unpriv.o
 libsbi-objs-y += sbi_expected_trap.o
 libsbi-objs-y += sbi_cppc.o
+libsbi-objs-y += sbi_vector.o
diff --git a/lib/sbi/sbi_vector.c b/lib/sbi/sbi_vector.c
new file mode 100644
index 00000000..497d7f94
--- /dev/null
+++ b/lib/sbi/sbi_vector.c
@@ -0,0 +1,215 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2026 RISCstar Solutions.
+ *
+ * Authors:
+ *	 Dave Patel <dave.patel@riscstar.com>
+ */
+
+#include <sbi/sbi_domain.h>
+#include <sbi/riscv_encoding.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/sbi_vector.h>
+#include <sbi/sbi_types.h>
+#include <sbi/sbi_hart.h>
+
+#ifdef OPENSBI_CC_SUPPORT_VECTOR
+
+static inline void vsetvl(ulong vl, ulong vtype)
+{
+    ulong tmp;
+
+    asm volatile(
+	".option push\n\t"
+	".option arch, +v\n\t"
+	"vsetvl %0, %1, %2\n\t"
+	".option pop\n\t"
+	: "=r"(tmp)
+	: "r"(vl), "r"(vtype)
+	: "memory");
+}
+
+static inline unsigned long vector_vlenb(void)
+{
+	unsigned long vlenb = 0;
+
+	asm volatile (
+		".option push\n\t"
+		".option arch, +v\n\t"
+		"csrr %0, vlenb\n\t"
+		".option pop\n\t"
+		: "=r"(vlenb)
+		:
+		: "memory");
+
+	return vlenb;
+}
+
+void sbi_vector_save(struct sbi_vector_context *dst)
+{
+	if (!dst)
+		return;
+
+#define READ_CSR(dst, csr) (				\
+	do {						\
+		asm volatile(				\
+			"	.option push\n\t"	\
+			"	.option arch, +v\n\t"	\
+			"	csrr %0, " #csr "\n\t"	\
+			"	.option pop\n\t"	\
+			:	"=r"(dst)		\
+			:				\
+			:	"memory");		\
+	} while (0))
+
+	/* Step 1: Save CSRs */
+	READ_CSR(dst->vtype,  vtype);
+	READ_CSR(dst->vl,     vl);
+	READ_CSR(dst->vcsr,   vcsr);
+	READ_CSR(dst->vstart, vstart);
+
+#undef READ_CSR
+
+	/*
+	 * Step 2: Set a known vector configuration before accessing registers.
+	 * This ensures the hardware is in a consistent state for save.
+	 */
+	vsetvl(dst->vl, dst->vtype);
+
+	ulong vlenb = vector_vlenb();
+	uint8_t *base = dst->vregs;
+
+	/* Step 3: Save vector registers */
+#define SAVE_VREG(i) (						\
+	asm volatile(						\
+		"	.option push\n\t"			\
+		"	.option arch, +v\n\t"			\
+		"	vse8.v v" #i ", (%0)\n\t"		\
+		"	.option pop\n\t"			\
+		::	"r"(base + (i) * vlenb)	: "memory"))
+
+	SAVE_VREG(0);
+	SAVE_VREG(1);
+	SAVE_VREG(2);
+	SAVE_VREG(3);
+	SAVE_VREG(4);
+	SAVE_VREG(5);
+	SAVE_VREG(6);
+	SAVE_VREG(7);
+	SAVE_VREG(8);
+	SAVE_VREG(9);
+	SAVE_VREG(10);
+	SAVE_VREG(11);
+	SAVE_VREG(12);
+	SAVE_VREG(13);
+	SAVE_VREG(14);
+	SAVE_VREG(15);
+	SAVE_VREG(16);
+	SAVE_VREG(17);
+	SAVE_VREG(18);
+	SAVE_VREG(19);
+	SAVE_VREG(20);
+	SAVE_VREG(21);
+	SAVE_VREG(22);
+	SAVE_VREG(23);
+	SAVE_VREG(24);
+	SAVE_VREG(25);
+	SAVE_VREG(26);
+	SAVE_VREG(27);
+	SAVE_VREG(28);
+	SAVE_VREG(29);
+	SAVE_VREG(30);
+	SAVE_VREG(31);
+
+#undef SAVE_VREG
+}
+
+void sbi_vector_restore(const struct sbi_vector_context *src)
+{
+	if (!src)
+		return;
+
+	const uint8_t *base = src->vregs;
+	ulong vlenb = vector_vlenb();
+
+	/*
+	 * Step 1: Set a known vector configuration BEFORE touching registers.
+	 * This avoids clobbering the restored CSRs later.
+	 */
+	vsetvl(src->vl, src->vtype);
+
+	/* Step 2: Restore vector registers */
+#define RESTORE_VREG(i) (					\
+	asm volatile(						\
+		"	.option push\n\t"			\
+		"	.option arch, +v\n\t"			\
+		"	vle8.v v" #i ", (%0)\n\t"		\
+		"	.option pop\n\t"			\
+		::	"r"(base + (i) * vlenb) : "memory"))
+
+	RESTORE_VREG(0);
+	RESTORE_VREG(1);
+	RESTORE_VREG(2);
+	RESTORE_VREG(3);
+	RESTORE_VREG(4);
+	RESTORE_VREG(5);
+	RESTORE_VREG(6);
+	RESTORE_VREG(7);
+	RESTORE_VREG(8);
+	RESTORE_VREG(9);
+	RESTORE_VREG(10);
+	RESTORE_VREG(11);
+	RESTORE_VREG(12);
+	RESTORE_VREG(13);
+	RESTORE_VREG(14);
+	RESTORE_VREG(15);
+	RESTORE_VREG(16);
+	RESTORE_VREG(17);
+	RESTORE_VREG(18);
+	RESTORE_VREG(19);
+	RESTORE_VREG(20);
+	RESTORE_VREG(21);
+	RESTORE_VREG(22);
+	RESTORE_VREG(23);
+	RESTORE_VREG(24);
+	RESTORE_VREG(25);
+	RESTORE_VREG(26);
+	RESTORE_VREG(27);
+	RESTORE_VREG(28);
+	RESTORE_VREG(29);
+	RESTORE_VREG(30);
+	RESTORE_VREG(31);
+#undef RESTORE_VREG
+
+	/* Step 3: Restore CSR's last */
+#define WRITE_CSR(csr, val) (			\
+	asm volatile(				\
+		"	.option push\n\t"	\
+		"	.option arch, +v\n\t"	\
+		"	csrw " #csr ", %0\n\t"	\
+		"	.option pop\n\t"	\
+		:				\
+		:	"r"(val)		\
+		:	"memory"))
+
+	/* Restore CSRs first */
+	WRITE_CSR(vtype,  src->vtype);
+	WRITE_CSR(vl,     src->vl);
+	WRITE_CSR(vcsr,   src->vcsr);
+	WRITE_CSR(vstart, src->vstart);
+#undef WRITE_CSR
+}
+
+#else
+
+void sbi_vector_save(struct sbi_vector_context *dst)
+{
+	return;
+}
+
+void sbi_vector_restore(const struct sbi_vector_context *src)
+{
+	return;
+}
+
+#endif /* OPENSBI_CC_SUPPORT_VECTOR */
--
2.43.0


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Re: [PATCH v3 1/3] lib: sbi: Add RISC-V vector context save/restore support

[Radim Krcmar]

2026-03-27T17:15:59+00:00, <dave.patel@riscstar.com>:
> From: Dave Patel <dave.patel@riscstar.com>
>
> Eager context switch: Add support for saving and restoring RISC-V vector
> extension state in OpenSBI. This introduces a per-hart vector context
> structure and helper routines to perform full context save and restore.
>
> The vector context includes vl, vtype, vcsr CSRs along with storage for all
> 32 vector registers. The register state is saved and restored using byte-wise
> vector load/store instructions (vse8.v/vle8.v), making the implementation
> independent of current SEW/LMUL configuration.

Using the whole register store/load (vs8r/vl8r) is more appropriate.
We must manipulate the whole architectural register file regardless of
what is configured by lower privileged modes.

(I think vse/vle shouldn't be used for the purpose of context-switching
 as it's too easy to introduce a security issue with them.)

> The implementation follows an eager context switching model where the entire
> vector state is saved and restored on every context switch. This provides a
> simple and deterministic mechanism without requiring lazy trap-based
> management.

The code below uses the lower privilege's vl/vtype, which means that we
do not save the entire vector register file, but only the subset that is
currently configured by lower-privileges.  This creates a side-channel.

> Notes:
> - The SBI_MAX_VLENB is configured using CONFIG_SBI_MAX_VLENB.
>
> Signed-off-by: Dave Patel <dave.patel@riscstar.com>
> ---
> diff --git a/include/sbi/sbi_vector.h b/include/sbi/sbi_vector.h
[...]
> +	/* Restore CSRs first */
> +	WRITE_CSR(vtype,  src->vtype);
> +	WRITE_CSR(vl,     src->vl);

vl and vtype are read-only registers... how does this work?

Thanks.
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[PATCH v3 0/3] Add eager FP and RISC-V vector context switching support

[dave.patel]

Hi Samuel et. al,
                Thank you for taking out time and reviewing the patches, there
has been some insightful comment and appreciate your inputs.

I have covered all your comments, please can you have a look and let me know.

Thanks and Regards,
Dave

Signed-off-by: Dave Patel <dave.patel@riscstar.com>

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[PATCH v3 1/3] lib: sbi: Add RISC-V vector context save/restore support

[dave.patel]

From: Dave Patel <dave.patel@riscstar.com>

Eager context switch: Add support for saving and restoring RISC-V vector
extension state in OpenSBI. This introduces a per-hart vector context
structure and helper routines to perform full context save and restore.

The vector context includes vl, vtype, vcsr CSRs along with storage for all
32 vector registers. The register state is saved and restored using byte-wise
vector load/store instructions (vse8.v/vle8.v), making the implementation
independent of current SEW/LMUL configuration.

The implementation follows an eager context switching model where the entire
vector state is saved and restored on every context switch. This provides a
simple and deterministic mechanism without requiring lazy trap-based
management.

Notes:
- The SBI_MAX_VLENB is configured using CONFIG_SBI_MAX_VLENB.

Signed-off-by: Dave Patel <dave.patel@riscstar.com>
---
 include/sbi/sbi_vector.h |  30 ++++++
 lib/sbi/Kconfig          |   4 +
 lib/sbi/objects.mk       |   1 +
 lib/sbi/sbi_vector.c     | 215 +++++++++++++++++++++++++++++++++++++++
 4 files changed, 250 insertions(+)
 create mode 100644 include/sbi/sbi_vector.h
 create mode 100644 lib/sbi/sbi_vector.c

diff --git a/include/sbi/sbi_vector.h b/include/sbi/sbi_vector.h
new file mode 100644
index 00000000..4ecfaa0b
--- /dev/null
+++ b/include/sbi/sbi_vector.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2026 RISCstar Solutions.
+ *
+ * Authors:
+ *   Dave Patel <dave.patel@riscstar.com>
+ */
+
+#ifndef __SBI_VECTOR_H__
+#define __SBI_VECTOR_H__
+
+#include <sbi/sbi_types.h>
+
+#define SBI_MAX_VLENB CONFIG_SBI_MAX_VLENB
+
+struct sbi_vector_context {
+	unsigned long vl;
+	unsigned long vtype;
+	unsigned long vcsr;
+	unsigned long vstart;
+
+	/* size depends on VLEN */
+	uint8_t vregs[32 * SBI_MAX_VLENB];
+};
+
+void sbi_vector_save(struct sbi_vector_context *dst);
+void sbi_vector_restore(const struct sbi_vector_context *src);
+
+#endif //__SBI_VECTOR_H__
+
diff --git a/lib/sbi/Kconfig b/lib/sbi/Kconfig
index 8479f861..b2432150 100644
--- a/lib/sbi/Kconfig
+++ b/lib/sbi/Kconfig
@@ -74,4 +74,8 @@ config SBI_ECALL_VIRQ
 	bool "VIRQ extension"
 	default y

+config SBI_MAX_VLENB
+	int "Vector VLENB size"
+	default 256
+
 endmenu
diff --git a/lib/sbi/objects.mk b/lib/sbi/objects.mk
index ea816e92..5c0caf39 100644
--- a/lib/sbi/objects.mk
+++ b/lib/sbi/objects.mk
@@ -106,3 +106,4 @@ libsbi-objs-y += sbi_trap_v_ldst.o
 libsbi-objs-y += sbi_unpriv.o
 libsbi-objs-y += sbi_expected_trap.o
 libsbi-objs-y += sbi_cppc.o
+libsbi-objs-y += sbi_vector.o
diff --git a/lib/sbi/sbi_vector.c b/lib/sbi/sbi_vector.c
new file mode 100644
index 00000000..497d7f94
--- /dev/null
+++ b/lib/sbi/sbi_vector.c
@@ -0,0 +1,215 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2026 RISCstar Solutions.
+ *
+ * Authors:
+ *	 Dave Patel <dave.patel@riscstar.com>
+ */
+
+#include <sbi/sbi_domain.h>
+#include <sbi/riscv_encoding.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/sbi_vector.h>
+#include <sbi/sbi_types.h>
+#include <sbi/sbi_hart.h>
+
+#ifdef OPENSBI_CC_SUPPORT_VECTOR
+
+static inline void vsetvl(ulong vl, ulong vtype)
+{
+    ulong tmp;
+
+    asm volatile(
+	".option push\n\t"
+	".option arch, +v\n\t"
+	"vsetvl %0, %1, %2\n\t"
+	".option pop\n\t"
+	: "=r"(tmp)
+	: "r"(vl), "r"(vtype)
+	: "memory");
+}
+
+static inline unsigned long vector_vlenb(void)
+{
+	unsigned long vlenb = 0;
+
+	asm volatile (
+		".option push\n\t"
+		".option arch, +v\n\t"
+		"csrr %0, vlenb\n\t"
+		".option pop\n\t"
+		: "=r"(vlenb)
+		:
+		: "memory");
+
+	return vlenb;
+}
+
+void sbi_vector_save(struct sbi_vector_context *dst)
+{
+	if (!dst)
+		return;
+
+#define READ_CSR(dst, csr) (				\
+	do {						\
+		asm volatile(				\
+			"	.option push\n\t"	\
+			"	.option arch, +v\n\t"	\
+			"	csrr %0, " #csr "\n\t"	\
+			"	.option pop\n\t"	\
+			:	"=r"(dst)		\
+			:				\
+			:	"memory");		\
+	} while (0))
+
+	/* Step 1: Save CSRs */
+	READ_CSR(dst->vtype,  vtype);
+	READ_CSR(dst->vl,     vl);
+	READ_CSR(dst->vcsr,   vcsr);
+	READ_CSR(dst->vstart, vstart);
+
+#undef READ_CSR
+
+	/*
+	 * Step 2: Set a known vector configuration before accessing registers.
+	 * This ensures the hardware is in a consistent state for save.
+	 */
+	vsetvl(dst->vl, dst->vtype);
+
+	ulong vlenb = vector_vlenb();
+	uint8_t *base = dst->vregs;
+
+	/* Step 3: Save vector registers */
+#define SAVE_VREG(i) (						\
+	asm volatile(						\
+		"	.option push\n\t"			\
+		"	.option arch, +v\n\t"			\
+		"	vse8.v v" #i ", (%0)\n\t"		\
+		"	.option pop\n\t"			\
+		::	"r"(base + (i) * vlenb)	: "memory"))
+
+	SAVE_VREG(0);
+	SAVE_VREG(1);
+	SAVE_VREG(2);
+	SAVE_VREG(3);
+	SAVE_VREG(4);
+	SAVE_VREG(5);
+	SAVE_VREG(6);
+	SAVE_VREG(7);
+	SAVE_VREG(8);
+	SAVE_VREG(9);
+	SAVE_VREG(10);
+	SAVE_VREG(11);
+	SAVE_VREG(12);
+	SAVE_VREG(13);
+	SAVE_VREG(14);
+	SAVE_VREG(15);
+	SAVE_VREG(16);
+	SAVE_VREG(17);
+	SAVE_VREG(18);
+	SAVE_VREG(19);
+	SAVE_VREG(20);
+	SAVE_VREG(21);
+	SAVE_VREG(22);
+	SAVE_VREG(23);
+	SAVE_VREG(24);
+	SAVE_VREG(25);
+	SAVE_VREG(26);
+	SAVE_VREG(27);
+	SAVE_VREG(28);
+	SAVE_VREG(29);
+	SAVE_VREG(30);
+	SAVE_VREG(31);
+
+#undef SAVE_VREG
+}
+
+void sbi_vector_restore(const struct sbi_vector_context *src)
+{
+	if (!src)
+		return;
+
+	const uint8_t *base = src->vregs;
+	ulong vlenb = vector_vlenb();
+
+	/*
+	 * Step 1: Set a known vector configuration BEFORE touching registers.
+	 * This avoids clobbering the restored CSRs later.
+	 */
+	vsetvl(src->vl, src->vtype);
+
+	/* Step 2: Restore vector registers */
+#define RESTORE_VREG(i) (					\
+	asm volatile(						\
+		"	.option push\n\t"			\
+		"	.option arch, +v\n\t"			\
+		"	vle8.v v" #i ", (%0)\n\t"		\
+		"	.option pop\n\t"			\
+		::	"r"(base + (i) * vlenb) : "memory"))
+
+	RESTORE_VREG(0);
+	RESTORE_VREG(1);
+	RESTORE_VREG(2);
+	RESTORE_VREG(3);
+	RESTORE_VREG(4);
+	RESTORE_VREG(5);
+	RESTORE_VREG(6);
+	RESTORE_VREG(7);
+	RESTORE_VREG(8);
+	RESTORE_VREG(9);
+	RESTORE_VREG(10);
+	RESTORE_VREG(11);
+	RESTORE_VREG(12);
+	RESTORE_VREG(13);
+	RESTORE_VREG(14);
+	RESTORE_VREG(15);
+	RESTORE_VREG(16);
+	RESTORE_VREG(17);
+	RESTORE_VREG(18);
+	RESTORE_VREG(19);
+	RESTORE_VREG(20);
+	RESTORE_VREG(21);
+	RESTORE_VREG(22);
+	RESTORE_VREG(23);
+	RESTORE_VREG(24);
+	RESTORE_VREG(25);
+	RESTORE_VREG(26);
+	RESTORE_VREG(27);
+	RESTORE_VREG(28);
+	RESTORE_VREG(29);
+	RESTORE_VREG(30);
+	RESTORE_VREG(31);
+#undef RESTORE_VREG
+
+	/* Step 3: Restore CSR's last */
+#define WRITE_CSR(csr, val) (			\
+	asm volatile(				\
+		"	.option push\n\t"	\
+		"	.option arch, +v\n\t"	\
+		"	csrw " #csr ", %0\n\t"	\
+		"	.option pop\n\t"	\
+		:				\
+		:	"r"(val)		\
+		:	"memory"))
+
+	/* Restore CSRs first */
+	WRITE_CSR(vtype,  src->vtype);
+	WRITE_CSR(vl,     src->vl);
+	WRITE_CSR(vcsr,   src->vcsr);
+	WRITE_CSR(vstart, src->vstart);
+#undef WRITE_CSR
+}
+
+#else
+
+void sbi_vector_save(struct sbi_vector_context *dst)
+{
+	return;
+}
+
+void sbi_vector_restore(const struct sbi_vector_context *src)
+{
+	return;
+}
+
+#endif /* OPENSBI_CC_SUPPORT_VECTOR */
--
2.43.0


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[PATCH v3 2/3] lib: sbi: Add floating-point context save/restore support.

[dave.patel]

From: Dave Patel <dave.patel@riscstar.com>

Add support for saving and restoring RISC-V floating-point (F/D) extension
state in OpenSBI. This introduces a floating-point context structure and
helper routines to perform full context save and restore.

The floating-point context includes storage for all 32 FPi registers (f0–f31)
along with the fcsr control and status register. The register state is saved
and restored using double-precision load/store instructions (fsd/fld), and
single-precision load/store instructions (fsw/flw) on an RV64 system with
F and D-extension support.

The implementation follows an eager context switching model where the entire
FP state is saved and restored on every context switch. This avoids the need
for trap-based lazy management and keeps the design simple and deterministic.

Signed-off-by: Dave Patel <dave.patel@riscstar.com>"
---
 include/sbi/sbi_fp.h |  36 ++++++++
 lib/sbi/objects.mk   |   1 +
 lib/sbi/sbi_fp.c     | 191 +++++++++++++++++++++++++++++++++++++++++++
 lib/sbi/sbi_vector.c |  24 +++---
 4 files changed, 240 insertions(+), 12 deletions(-)
 create mode 100644 include/sbi/sbi_fp.h
 create mode 100644 lib/sbi/sbi_fp.c

diff --git a/include/sbi/sbi_fp.h b/include/sbi/sbi_fp.h
new file mode 100644
index 00000000..8079bb3b
--- /dev/null
+++ b/include/sbi/sbi_fp.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2026 RISCstar Solutions.
+ *
+ * Authors:
+ *   Dave Patel <dave.patel@riscstar.com>
+ */
+#ifndef __SBI_FP_H__
+#define __SBI_FP_H__
+
+#include <sbi/riscv_encoding.h>
+#include <sbi/sbi_types.h>
+
+#if defined(__riscv_f) || defined(__riscv_d)
+
+#include <stdint.h>
+
+struct sbi_fp_context {
+#if __riscv_d
+	uint64_t f[32];
+#else
+	uint32_t f[32];
+#endif
+	uint32_t fcsr;
+} __aligned(16);
+
+#else /* No FP (e.g., Zve32x) */
+
+struct sbi_fp_context { };
+
+#endif //defined(__riscv_f) || defined(__riscv_d)
+
+void sbi_fp_save(struct sbi_fp_context *dst);
+void sbi_fp_restore(const struct sbi_fp_context *src);
+
+#endif //__SBI_VECTOR_H__
diff --git a/lib/sbi/objects.mk b/lib/sbi/objects.mk
index 5c0caf39..ca560c2e 100644
--- a/lib/sbi/objects.mk
+++ b/lib/sbi/objects.mk
@@ -107,3 +107,4 @@ libsbi-objs-y += sbi_unpriv.o
 libsbi-objs-y += sbi_expected_trap.o
 libsbi-objs-y += sbi_cppc.o
 libsbi-objs-y += sbi_vector.o
+libsbi-objs-y += sbi_fp.o
diff --git a/lib/sbi/sbi_fp.c b/lib/sbi/sbi_fp.c
new file mode 100644
index 00000000..5d72b72e
--- /dev/null
+++ b/lib/sbi/sbi_fp.c
@@ -0,0 +1,191 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2026 RISCstar Solutions.
+ *
+ * Authors:
+ *   Dave Patel <dave.patel@riscstar.com>
+ */
+
+#include <sbi/riscv_asm.h>
+#include <sbi/riscv_encoding.h>
+#include <sbi/sbi_fp.h>
+
+#if defined(__riscv_f) || defined(__riscv_d)
+
+void sbi_fp_save(struct sbi_fp_context *dst)
+{
+	if (!dst)
+		return;
+
+#if defined(__riscv_d)
+	asm volatile(
+		"fsd f0,  0(%0)\n"
+		"fsd f1,  8(%0)\n"
+		"fsd f2,  16(%0)\n"
+		"fsd f3,  24(%0)\n"
+		"fsd f4,  32(%0)\n"
+		"fsd f5,  40(%0)\n"
+		"fsd f6,  48(%0)\n"
+		"fsd f7,  56(%0)\n"
+		"fsd f8,  64(%0)\n"
+		"fsd f9,  72(%0)\n"
+		"fsd f10, 80(%0)\n"
+		"fsd f11, 88(%0)\n"
+		"fsd f12, 96(%0)\n"
+		"fsd f13, 104(%0)\n"
+		"fsd f14, 112(%0)\n"
+		"fsd f15, 120(%0)\n"
+		"fsd f16, 128(%0)\n"
+		"fsd f17, 136(%0)\n"
+		"fsd f18, 144(%0)\n"
+		"fsd f19, 152(%0)\n"
+		"fsd f20, 160(%0)\n"
+		"fsd f21, 168(%0)\n"
+		"fsd f22, 176(%0)\n"
+		"fsd f23, 184(%0)\n"
+		"fsd f24, 192(%0)\n"
+		"fsd f25, 200(%0)\n"
+		"fsd f26, 208(%0)\n"
+		"fsd f27, 216(%0)\n"
+		"fsd f28, 224(%0)\n"
+		"fsd f29, 232(%0)\n"
+		"fsd f30, 240(%0)\n"
+		"fsd f31, 248(%0)\n"
+		:
+		: "r"(dst->f)
+		: "memory"
+	);
+#else
+	asm volatile(
+		"fsw f0,  0(%0)\n"
+		"fsw f1,  4(%0)\n"
+		"fsw f2,  8(%0)\n"
+		"fsw f3,  12(%0)\n"
+		"fsw f4,  16(%0)\n"
+		"fsw f5,  20(%0)\n"
+		"fsw f6,  24(%0)\n"
+		"fsw f7,  28(%0)\n"
+		"fsw f8,  32(%0)\n"
+		"fsw f9,  36(%0)\n"
+		"fsw f10, 40(%0)\n"
+		"fsw f11, 44(%0)\n"
+		"fsw f12, 48(%0)\n"
+		"fsw f13, 52(%0)\n"
+		"fsw f14, 56(%0)\n"
+		"fsw f15, 60(%0)\n"
+		"fsw f16, 64(%0)\n"
+		"fsw f17, 68(%0)\n"
+		"fsw f18, 72(%0)\n"
+		"fsw f19, 76(%0)\n"
+		"fsw f20, 80(%0)\n"
+		"fsw f21, 84(%0)\n"
+		"fsw f22, 88(%0)\n"
+		"fsw f23, 92(%0)\n"
+		"fsw f24, 96(%0)\n"
+		"fsw f25, 100(%0)\n"
+		"fsw f26, 104(%0)\n"
+		"fsw f27, 108(%0)\n"
+		"fsw f28, 112(%0)\n"
+		"fsw f29, 116(%0)\n"
+		"fsw f30, 120(%0)\n"
+		"fsw f31, 124(%0)\n"
+		:
+		: "r"(dst->f)
+		: "memory"
+	);
+#endif //__riscv_d
+
+	dst->fcsr = csr_read(CSR_FCSR);
+}
+
+void sbi_fp_restore(const struct sbi_fp_context *src)
+{
+	if (!src)
+		return;
+
+#if defined(__riscv_d)
+	asm volatile(
+		"fld f0,  0(%0)\n"
+		"fld f1,  8(%0)\n"
+		"fld f2,  16(%0)\n"
+		"fld f3,  24(%0)\n"
+		"fld f4,  32(%0)\n"
+		"fld f5,  40(%0)\n"
+		"fld f6,  48(%0)\n"
+		"fld f7,  56(%0)\n"
+		"fld f8,  64(%0)\n"
+		"fld f9,  72(%0)\n"
+		"fld f10, 80(%0)\n"
+		"fld f11, 88(%0)\n"
+		"fld f12, 96(%0)\n"
+		"fld f13, 104(%0)\n"
+		"fld f14, 112(%0)\n"
+		"fld f15, 120(%0)\n"
+		"fld f16, 128(%0)\n"
+		"fld f17, 136(%0)\n"
+		"fld f18, 144(%0)\n"
+		"fld f19, 152(%0)\n"
+		"fld f20, 160(%0)\n"
+		"fld f21, 168(%0)\n"
+		"fld f22, 176(%0)\n"
+		"fld f23, 184(%0)\n"
+		"fld f24, 192(%0)\n"
+		"fld f25, 200(%0)\n"
+		"fld f26, 208(%0)\n"
+		"fld f27, 216(%0)\n"
+		"fld f28, 224(%0)\n"
+		"fld f29, 232(%0)\n"
+		"fld f30, 240(%0)\n"
+		"fld f31, 248(%0)\n"
+		:
+		: "r"(src->f)
+		: "memory"
+	);
+#else
+
+	asm volatile(
+		"flw f0,   0(%0)\n"
+		"flw f1,   4(%0)\n"
+		"flw f2,   8(%0)\n"
+		"flw f3,  12(%0)\n"
+		"flw f4,  16(%0)\n"
+		"flw f5,  20(%0)\n"
+		"flw f6,  24(%0)\n"
+		"flw f7,  28(%0)\n"
+		"flw f8,  32(%0)\n"
+		"flw f9,  36(%0)\n"
+		"flw f10, 40(%0)\n"
+		"flw f11, 44(%0)\n"
+		"flw f12, 48(%0)\n"
+		"flw f13, 52(%0)\n"
+		"flw f14, 56(%0)\n"
+		"flw f15, 60(%0)\n"
+		"flw f16, 64(%0)\n"
+		"flw f17, 68(%0)\n"
+		"flw f18, 72(%0)\n"
+		"flw f19, 76(%0)\n"
+		"flw f20, 80(%0)\n"
+		"flw f21, 84(%0)\n"
+		"flw f22, 88(%0)\n"
+		"flw f23, 92(%0)\n"
+		"flw f24, 96(%0)\n"
+		"flw f25, 100(%0)\n"
+		"flw f26, 104(%0)\n"
+		"flw f27, 108(%0)\n"
+		"flw f28, 112(%0)\n"
+		"flw f29, 116(%0)\n"
+		"flw f30, 120(%0)\n"
+		"flw f31, 124(%0)\n"
+		:
+		: "r"(src->f)
+		: "memory"
+	);
+
+#endif
+
+	csr_write(CSR_FCSR, src->fcsr);
+}
+#else
+void sbi_fp_save(struct sbi_fp_context *dst) {}
+void sbi_fp_restore(const struct sbi_fp_context *src) {}
+#endif // FP present
diff --git a/lib/sbi/sbi_vector.c b/lib/sbi/sbi_vector.c
index 497d7f94..5a3f34d7 100644
--- a/lib/sbi/sbi_vector.c
+++ b/lib/sbi/sbi_vector.c
@@ -50,8 +50,8 @@ void sbi_vector_save(struct sbi_vector_context *dst)
 	if (!dst)
 		return;

-#define READ_CSR(dst, csr) (				\
-	do {						\
+#define READ_CSR(dst, csr) 				\
+	{						\
 		asm volatile(				\
 			"	.option push\n\t"	\
 			"	.option arch, +v\n\t"	\
@@ -60,7 +60,7 @@ void sbi_vector_save(struct sbi_vector_context *dst)
 			:	"=r"(dst)		\
 			:				\
 			:	"memory");		\
-	} while (0))
+	}

 	/* Step 1: Save CSRs */
 	READ_CSR(dst->vtype,  vtype);
@@ -80,13 +80,13 @@ void sbi_vector_save(struct sbi_vector_context *dst)
 	uint8_t *base = dst->vregs;

 	/* Step 3: Save vector registers */
-#define SAVE_VREG(i) (						\
-	asm volatile(						\
+#define SAVE_VREG(i) 						\
+	{asm volatile(						\
 		"	.option push\n\t"			\
 		"	.option arch, +v\n\t"			\
 		"	vse8.v v" #i ", (%0)\n\t"		\
 		"	.option pop\n\t"			\
-		::	"r"(base + (i) * vlenb)	: "memory"))
+		::	"r"(base + (i) * vlenb)	: "memory"); }

 	SAVE_VREG(0);
 	SAVE_VREG(1);
@@ -139,13 +139,13 @@ void sbi_vector_restore(const struct sbi_vector_context *src)
 	vsetvl(src->vl, src->vtype);

 	/* Step 2: Restore vector registers */
-#define RESTORE_VREG(i) (					\
-	asm volatile(						\
+#define RESTORE_VREG(i) 					\
+	{asm volatile(						\
 		"	.option push\n\t"			\
 		"	.option arch, +v\n\t"			\
 		"	vle8.v v" #i ", (%0)\n\t"		\
 		"	.option pop\n\t"			\
-		::	"r"(base + (i) * vlenb) : "memory"))
+		::	"r"(base + (i) * vlenb) : "memory"); }

 	RESTORE_VREG(0);
 	RESTORE_VREG(1);
@@ -182,15 +182,15 @@ void sbi_vector_restore(const struct sbi_vector_context *src)
 #undef RESTORE_VREG

 	/* Step 3: Restore CSR's last */
-#define WRITE_CSR(csr, val) (			\
-	asm volatile(				\
+#define WRITE_CSR(csr, val) 			\
+	{ asm volatile(				\
 		"	.option push\n\t"	\
 		"	.option arch, +v\n\t"	\
 		"	csrw " #csr ", %0\n\t"	\
 		"	.option pop\n\t"	\
 		:				\
 		:	"r"(val)		\
-		:	"memory"))
+		:	"memory"); }

 	/* Restore CSRs first */
 	WRITE_CSR(vtype,  src->vtype);
--
2.43.0


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[PATCH v3 3/3] lib: sbi: domain FP/Vector context support for context switch

[dave.patel]

From: Dave Patel <dave.patel@riscstar.com>

This patch adds proper support for per-domain floating-point (FP) and
vector (V) contexts in the domain context switch logic. Each domain
now maintains its own FP and vector state, which is saved and restored
during domain switches.

Changes include:

- Added `fp_ctx` and `vec_ctx` members to `struct sbi_domain`.
- Introduced `sbi_vector_domain_init` for vlen check
  to allocate and free per-domain FP and vector context.
- Modified `sbi_domain_register()` to initialize FP/Vector context per domain.
- Updated `switch_to_next_domain_context()` to save/restore FP and vector
  contexts safely:
    - Ensures FS/VS fields in `mstatus` are enabled (set to Initial) only if Off.
    - Restores original FS/VS bits after context switch.
    - Adds NULL checks to handle domains without FP or Vector extensions.
- Updated domain context deinit to free FP and vector contexts per domain.
- Added runtime checks for FP and vector extensions where needed.
- Corrected handling of MSTATUS FS/VS bits to avoid unsafe full-bit writes.

This improves support for multi-domain systems with FP and Vector
extensions, and prevents corruption of FP/Vector state during domain
switches.

Signed-off-by: Dave Patel <dave.patel@riscstar.com>
---
 include/sbi/sbi_domain.h     |  6 +++++
 include/sbi/sbi_fp.h         | 13 +----------
 include/sbi/sbi_vector.h     |  4 ++++
 lib/sbi/sbi_domain.c         |  6 +++++
 lib/sbi/sbi_domain_context.c | 12 ++++++++++
 lib/sbi/sbi_fp.c             |  6 +++++
 lib/sbi/sbi_vector.c         | 43 ++++++++++++++++++++++++++----------
 7 files changed, 66 insertions(+), 24 deletions(-)

diff --git a/include/sbi/sbi_domain.h b/include/sbi/sbi_domain.h
index 882b62c2..318d3a9a 100644
--- a/include/sbi/sbi_domain.h
+++ b/include/sbi/sbi_domain.h
@@ -16,6 +16,8 @@
 #include <sbi/sbi_hartmask.h>
 #include <sbi/sbi_domain_context.h>
 #include <sbi/sbi_domain_data.h>
+#include <sbi/sbi_vector.h>
+#include <sbi/sbi_fp.h>

 struct sbi_scratch;

@@ -217,6 +219,10 @@ struct sbi_domain {
 	bool fw_region_inited;
 	/** per-domain wired-IRQ courier state */
 	void *virq_priv;
+	/** per-domain float context state */
+	struct sbi_fp_context fp_ctx;
+	/** per-domain vector context state */
+	struct sbi_vector_context vec_ctx;
 };

 /** The root domain instance */
diff --git a/include/sbi/sbi_fp.h b/include/sbi/sbi_fp.h
index 8079bb3b..962150a3 100644
--- a/include/sbi/sbi_fp.h
+++ b/include/sbi/sbi_fp.h
@@ -8,13 +8,8 @@
 #ifndef __SBI_FP_H__
 #define __SBI_FP_H__

-#include <sbi/riscv_encoding.h>
 #include <sbi/sbi_types.h>

-#if defined(__riscv_f) || defined(__riscv_d)
-
-#include <stdint.h>
-
 struct sbi_fp_context {
 #if __riscv_d
 	uint64_t f[32];
@@ -22,13 +17,7 @@ struct sbi_fp_context {
 	uint32_t f[32];
 #endif
 	uint32_t fcsr;
-} __aligned(16);
-
-#else /* No FP (e.g., Zve32x) */
-
-struct sbi_fp_context { };
-
-#endif //defined(__riscv_f) || defined(__riscv_d)
+};

 void sbi_fp_save(struct sbi_fp_context *dst);
 void sbi_fp_restore(const struct sbi_fp_context *src);
diff --git a/include/sbi/sbi_vector.h b/include/sbi/sbi_vector.h
index 4ecfaa0b..9ae76b00 100644
--- a/include/sbi/sbi_vector.h
+++ b/include/sbi/sbi_vector.h
@@ -10,6 +10,9 @@
 #define __SBI_VECTOR_H__

 #include <sbi/sbi_types.h>
+#include <sbi/sbi_domain.h>
+#include <sbi/sbi_error.h>
+#include <sbi/sbi_console.h>

 #define SBI_MAX_VLENB CONFIG_SBI_MAX_VLENB

@@ -25,6 +28,7 @@ struct sbi_vector_context {

 void sbi_vector_save(struct sbi_vector_context *dst);
 void sbi_vector_restore(const struct sbi_vector_context *src);
+int sbi_vector_domain_init(void);

 #endif //__SBI_VECTOR_H__

diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c
index 498a1d56..424204eb 100644
--- a/lib/sbi/sbi_domain.c
+++ b/lib/sbi/sbi_domain.c
@@ -19,6 +19,8 @@
 #include <sbi/sbi_scratch.h>
 #include <sbi/sbi_string.h>
 #include <sbi/sbi_virq.h>
+#include <sbi/sbi_vector.h>
+#include <sbi/sbi_fp.h>

 SBI_LIST_HEAD(domain_list);

@@ -1007,6 +1009,10 @@ int sbi_domain_init(struct sbi_scratch *scratch, u32 cold_hartid)
 	if (rc)
 		goto fail_free_root_hmask;

+	rc = sbi_vector_domain_init();
+	if (rc)
+		goto fail_free_root_hmask;
+
 	return 0;

 fail_free_root_hmask:
diff --git a/lib/sbi/sbi_domain_context.c b/lib/sbi/sbi_domain_context.c
index 158f4990..f646c7d4 100644
--- a/lib/sbi/sbi_domain_context.c
+++ b/lib/sbi/sbi_domain_context.c
@@ -18,6 +18,9 @@
 #include <sbi/sbi_domain_context.h>
 #include <sbi/sbi_platform.h>
 #include <sbi/sbi_trap.h>
+#include <sbi/sbi_vector.h>
+#include <sbi/sbi_fp.h>
+

 /** Context representation for a hart within a domain */
 struct hart_context {
@@ -143,6 +146,15 @@ static int switch_to_next_domain_context(struct hart_context *ctx,
 	if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSQOSID))
 		ctx->srmcfg	= csr_swap(CSR_SRMCFG, dom_ctx->srmcfg);

+	/* Make sure FS and VS is on before context switch */
+	csr_set(CSR_MSTATUS, MSTATUS_FS | MSTATUS_VS);
+
+	/* Eager context switch F and V */
+	sbi_fp_save(&current_dom->fp_ctx);
+	sbi_fp_restore(&target_dom->fp_ctx);
+	sbi_vector_save(&current_dom->vec_ctx);
+	sbi_vector_restore(&target_dom->vec_ctx);
+
 	/* Save current trap state and restore target domain's trap state */
 	trap_ctx = sbi_trap_get_context(scratch);
 	sbi_memcpy(&ctx->trap_ctx, trap_ctx, sizeof(*trap_ctx));
diff --git a/lib/sbi/sbi_fp.c b/lib/sbi/sbi_fp.c
index 5d72b72e..9772d359 100644
--- a/lib/sbi/sbi_fp.c
+++ b/lib/sbi/sbi_fp.c
@@ -7,8 +7,11 @@
  */

 #include <sbi/riscv_asm.h>
+#include <sbi/sbi_heap.h>
 #include <sbi/riscv_encoding.h>
 #include <sbi/sbi_fp.h>
+#include <sbi/sbi_error.h>
+#include <sbi/sbi_console.h>

 #if defined(__riscv_f) || defined(__riscv_d)

@@ -185,7 +188,10 @@ void sbi_fp_restore(const struct sbi_fp_context *src)

 	csr_write(CSR_FCSR, src->fcsr);
 }
+
 #else
+
 void sbi_fp_save(struct sbi_fp_context *dst) {}
 void sbi_fp_restore(const struct sbi_fp_context *src) {}
+
 #endif // FP present
diff --git a/lib/sbi/sbi_vector.c b/lib/sbi/sbi_vector.c
index 5a3f34d7..5877c373 100644
--- a/lib/sbi/sbi_vector.c
+++ b/lib/sbi/sbi_vector.c
@@ -12,21 +12,23 @@
 #include <sbi/sbi_vector.h>
 #include <sbi/sbi_types.h>
 #include <sbi/sbi_hart.h>
+#include <sbi/sbi_heap.h>

 #ifdef OPENSBI_CC_SUPPORT_VECTOR
+#define VLEN_MAX 65536

 static inline void vsetvl(ulong vl, ulong vtype)
 {
-    ulong tmp;
-
-    asm volatile(
-	".option push\n\t"
-	".option arch, +v\n\t"
-	"vsetvl %0, %1, %2\n\t"
-	".option pop\n\t"
-	: "=r"(tmp)
-	: "r"(vl), "r"(vtype)
-	: "memory");
+	ulong tmp;
+
+	asm volatile(
+		".option push\n\t"
+		".option arch, +v\n\t"
+		"vsetvl %0, %1, %2\n\t"
+		".option pop\n\t"
+		: "=r"(tmp)
+		: "r"(vl), "r"(vtype)
+		: "memory");
 }

 static inline unsigned long vector_vlenb(void)
@@ -64,7 +66,7 @@ void sbi_vector_save(struct sbi_vector_context *dst)

 	/* Step 1: Save CSRs */
 	READ_CSR(dst->vtype,  vtype);
-	READ_CSR(dst->vl,     vl);
+	READ_CSR(dst->vl,	  vl);
 	READ_CSR(dst->vcsr,   vcsr);
 	READ_CSR(dst->vstart, vstart);

@@ -194,12 +196,24 @@ void sbi_vector_restore(const struct sbi_vector_context *src)

 	/* Restore CSRs first */
 	WRITE_CSR(vtype,  src->vtype);
-	WRITE_CSR(vl,     src->vl);
+	WRITE_CSR(vl,	  src->vl);
 	WRITE_CSR(vcsr,   src->vcsr);
 	WRITE_CSR(vstart, src->vstart);
 #undef WRITE_CSR
 }

+int sbi_vector_domain_init(void)
+{
+	ulong vlenb = vector_vlenb();
+
+	if (vlenb > SBI_MAX_VLENB) {
+		sbi_printf("[Vector ERR:] vlenb range error\n");
+		return SBI_ERR_BAD_RANGE;
+	}
+
+	return SBI_OK;
+}
+
 #else

 void sbi_vector_save(struct sbi_vector_context *dst)
@@ -212,4 +226,9 @@ void sbi_vector_restore(const struct sbi_vector_context *src)
 	return;
 }

+int sbi_vector_domain_init(void)
+{
+	return SBI_OK;
+
 #endif /* OPENSBI_CC_SUPPORT_VECTOR */
+
--
2.43.0


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Re: [PATCH v3 1/3] lib: sbi: Add RISC-V vector context save/restore support

[Radim Krčmář]

2026-03-31T06:58:55+01:00, <dave.patel@riscstar.com>:
> From: Dave Patel <dave.patel@riscstar.com>
>
> Eager context switch: Add support for saving and restoring RISC-V vector
> extension state in OpenSBI. This introduces a per-hart vector context
> structure and helper routines to perform full context save and restore.
>
> The vector context includes vl, vtype, vcsr CSRs along with storage for all
> 32 vector registers. The register state is saved and restored using byte-wise
> vector load/store instructions (vse8.v/vle8.v), making the implementation
> independent of current SEW/LMUL configuration.
>
> The implementation follows an eager context switching model where the entire
> vector state is saved and restored on every context switch. This provides a
> simple and deterministic mechanism without requiring lazy trap-based
> management.
>
> Notes:
> - The SBI_MAX_VLENB is configured using CONFIG_SBI_MAX_VLENB.
>
> Signed-off-by: Dave Patel <dave.patel@riscstar.com>
> ---

You missed my comment on [v2 1/3]:
https://lore.kernel.org/opensbi/DHG4IUERGFUV.3TT9CFPZ9YEDG@qti.qualcomm.com/

The two points are:
1. Possible cross-domain data access.
2. Writes to read-only CSRs.

Thanks.

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Re: [PATCH v3 2/3] lib: sbi: Add floating-point context save/restore support.

[Radim Krčmář]

2026-03-31T06:58:56+01:00, <dave.patel@riscstar.com>:
> From: Dave Patel <dave.patel@riscstar.com>
>
> Add support for saving and restoring RISC-V floating-point (F/D) extension
> state in OpenSBI. This introduces a floating-point context structure and
> helper routines to perform full context save and restore.
>
> The floating-point context includes storage for all 32 FPi registers (f0–f31)
> along with the fcsr control and status register. The register state is saved
> and restored using double-precision load/store instructions (fsd/fld), and
> single-precision load/store instructions (fsw/flw) on an RV64 system with
> F and D-extension support.
>
> The implementation follows an eager context switching model where the entire
> FP state is saved and restored on every context switch. This avoids the need
> for trap-based lazy management and keeps the design simple and deterministic.
>
> Signed-off-by: Dave Patel <dave.patel@riscstar.com>"
> ---
> diff --git a/lib/sbi/sbi_vector.c b/lib/sbi/sbi_vector.c
> @@ -50,8 +50,8 @@ void sbi_vector_save(struct sbi_vector_context *dst)
>  	if (!dst)
>  		return;
>
> -#define READ_CSR(dst, csr) (				\
> -	do {						\
> +#define READ_CSR(dst, csr) 				\
> +	{						\

Please, change the first patch instead of fixing the bug here.

(Btw. "({ ... })" is a superior macro wrapper.)

Thanks.

[...]

> -	} while (0))
> +	}

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Re: [PATCH v3 3/3] lib: sbi: domain FP/Vector context support for context switch

[Radim Krčmář]

2026-03-31T06:58:57+01:00, <dave.patel@riscstar.com>:
> From: Dave Patel <dave.patel@riscstar.com>
>
> This patch adds proper support for per-domain floating-point (FP) and
> vector (V) contexts in the domain context switch logic. Each domain
> now maintains its own FP and vector state, which is saved and restored
> during domain switches.
>
> Changes include:
>
> - Added `fp_ctx` and `vec_ctx` members to `struct sbi_domain`.
> - Introduced `sbi_vector_domain_init` for vlen check
>   to allocate and free per-domain FP and vector context.
> - Modified `sbi_domain_register()` to initialize FP/Vector context per domain.
> - Updated `switch_to_next_domain_context()` to save/restore FP and vector
>   contexts safely:
>     - Ensures FS/VS fields in `mstatus` are enabled (set to Initial) only if Off.
>     - Restores original FS/VS bits after context switch.
>     - Adds NULL checks to handle domains without FP or Vector extensions.
> - Updated domain context deinit to free FP and vector contexts per domain.
> - Added runtime checks for FP and vector extensions where needed.
> - Corrected handling of MSTATUS FS/VS bits to avoid unsafe full-bit writes.
>
> This improves support for multi-domain systems with FP and Vector
> extensions, and prevents corruption of FP/Vector state during domain
> switches.
>
> Signed-off-by: Dave Patel <dave.patel@riscstar.com>
> ---
> diff --git a/include/sbi/sbi_fp.h b/include/sbi/sbi_fp.h
> @@ -8,13 +8,8 @@
>  #ifndef __SBI_FP_H__
>  #define __SBI_FP_H__
>
> -#include <sbi/riscv_encoding.h>
>  #include <sbi/sbi_types.h>
>
> -#if defined(__riscv_f) || defined(__riscv_d)
> -
> -#include <stdint.h>
> -
>  struct sbi_fp_context {
>  #if __riscv_d
>  	uint64_t f[32];
> @@ -22,13 +17,7 @@ struct sbi_fp_context {
>  	uint32_t f[32];
>  #endif
>  	uint32_t fcsr;
> -} __aligned(16);
> -
> -#else /* No FP (e.g., Zve32x) */
> -
> -struct sbi_fp_context { };
> -
> -#endif //defined(__riscv_f) || defined(__riscv_d)
> +};

Similar comment as to [2/3]: these should have been introduced earlier.

(There is a lot of other random artifacts in the patch.)

> diff --git a/lib/sbi/sbi_domain_context.c b/lib/sbi/sbi_domain_context.c
> @@ -143,6 +146,15 @@ static int switch_to_next_domain_context(struct hart_context *ctx,
> +	/* Make sure FS and VS is on before context switch */
> +	csr_set(CSR_MSTATUS, MSTATUS_FS | MSTATUS_VS);

Where is the ctx->sstatus restored to CSR_SSTATUS?

Thanks.

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