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boundary="===============6698134897843493998==" Sender: "opensbi" Errors-To: opensbi-bounces+opensbi=archiver.kernel.org@lists.infradead.org --===============6698134897843493998== Content-Type: multipart/signed; boundary=f1d28fe9af8988741c87ebf7a563e6f8b968f4d28832d411b66014d0b77a; micalg=pgp-sha512; protocol="application/pgp-signature" --f1d28fe9af8988741c87ebf7a563e6f8b968f4d28832d411b66014d0b77a Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 On Fri Aug 21, 2026 at 10:33 PM +08, Heinrich Schuchardt wrote: > On 8/18/26 03:14, Troy Mitchell wrote: >> Add initial OpenSBI platform support for the SpacemiT K3 SoC. K3 has >> 16 harts split across four clusters: eight X100 harts in C0/C1 and >> eight A100 harts in C2/C3. >>=20 >> The main upstream integration constraint is that K3 is heterogeneous at >> the ISA level. The CPU device tree used for testing exposes the same >> non-H standard extensions for X100 and A100. X100 additionally exposes H >> and the related Sha, Shcounterenw, Shgatpa, Shtvala, Shvsatpa, >> Shvstvala, and Shvstvecd extensions. X100 has a 256-bit VLEN, while >> A100 has a 1024-bit VLEN. A100 also implements the vendor-specific >> SpacemiT IME and FP8 AI extensions, which OpenSBI does not inspect or >> use. >>=20 >> At the base of this series, OpenSBI selects the expected-trap handler >> once from the cold-boot hart and reuses it globally. An X100 cold-boot >> hart would therefore make an A100 hart use the H-aware handler, which >> accesses mtval2 and mtinst even though A100 does not implement H. Select >> the handler from the current hart instead. An audit of the remaining >> extension-dependent paths found that ISA extensions and detected CSR >> features are stored per-hart, the generic FDT parser visits every hart, >> and vector code reads the current hart's VLENB. The K3 CPU device tree >> also exposes the same counter and timer extensions on both core types. >> No other cold-boot-hart-derived ISA selection was found. >>=20 >> K1 and K3 share vendor cache-control CSRs, PMU idle fields, cluster >> sizing, and the CCI-550 programming sequence, but their CCI topology, >> boot flow, and HSM support differ. Factor only the common definitions an= d >> CCI helper so K3 does not depend on K1 and the K1 encoded values and >> behavior remain unchanged. Run per-hart register setup from >> nascent_init() rather than the policy-only cold_boot_allowed() hook. >>=20 >> On K3, the cold-boot hart programs the four cluster warm-boot vectors, >> enables CCI snoop and DVM requests, prevents WFI from powering down core= s >> or clusters, and wakes the secondary harts. A bounded wait prevents a >> non-responsive secondary hart from stalling boot indefinitely. Each hart >> programs its own PMA, cache, snooping, and prefetch state, with X100 har= ts >> also enabling H. The warm-boot entry establishes cache coherency before >> entering common code so secondary harts can observe state published by >> the cold-boot hart. >>=20 >> Runtime validation used the SpacemiT K3 SDK. The UART at 115200 baud >> showed OpenSBI and U-Boot starting successfully, followed by Linux >> bringing all 16 harts online. The series has also been build-tested with= : >>=20 >> - the generic default configuration >> - a K1 configuration with K3 disabled and the SpacemiT HSM driver >> - a K3 configuration with K1 and the SpacemiT HSM driver disabled >>=20 >> To reproduce the runtime test, build this OpenSBI tree at the address >> where the SDK loads it, then copy the resulting firmware into the SDK >> output directory: >>=20 >> K3_SDK_DIR=3D/path/to/k3-sdk >> make O=3Dbuild-k3 CROSS_COMPILE=3Driscv64-linux-gnu- PLATFORM=3Dgener= ic \ >> FW_TEXT_START=3D0x100000000 >> cp build-k3/platform/generic/firmware/fw_dynamic.bin \ >> "$K3_SDK_DIR/output/fw_dynamic.bin" >>=20 >> Before rebuilding U-Boot, update the UART0 node in the K3 board DT >> selected by SPL and passed to OpenSBI. The SDK describes it only as >> "ns16550", so upstream OpenSBI initializes it without UART_CAP_UUE and >> writes 0x00 to UART_IER. The K3 UART requires UART_IER_UUE (bit 6). >> Change the node in uboot-2022.10/arch/riscv/dts/k3.dtsi to: >>=20 >> uart0: uart@d4017000 { >> ... >> compatible =3D "spacemit,k1-uart", "intel,xscale-uart", >> "ns16550"; >> ... >> }; >>=20 >> The compatible order is significant. Upstream OpenSBI skips the vendor >> string, then matches "intel,xscale-uart", which selects UART_CAP_UUE and >> writes 0x40 to UART_IER. The final "ns16550" remains a generic fallback. >> This is the DT used for the successful boot test. >>=20 >> With output/fw_dynamic.bin already present, rebuild U-Boot. The SDK >> preserves that OpenSBI binary and packages it with U-Boot: >>=20 >> make -C "$K3_SDK_DIR" uboot > > The SpacemiT firmware is developing fast. Please, indicate the exact=20 > version by commit hash and repo url for buildroot, U-Boot, esos, EDK II,= =20 > Linux or any other repos that are needed for testing. Will add the exact commit hashes in the next revision. --=20 Troy Mitchell --f1d28fe9af8988741c87ebf7a563e6f8b968f4d28832d411b66014d0b77a Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iIMEABYKACsWIQSL4Ay2cExaPXAQcU2YCe+A+TM0LwUCao+mDg0caUB0cm95LXku b3JnAAoJEJgJ74D5MzQvHoYBAKlOJmXF63VaEuCgIFx02YdT9yH/gbndmboOasLz CL4EAQCCxK/ja3QvFxQMGCOzqlD4KYuvBQETJdphMH9UDX2yAQ== =PpTk -----END PGP SIGNATURE----- --f1d28fe9af8988741c87ebf7a563e6f8b968f4d28832d411b66014d0b77a-- --===============6698134897843493998== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline -- opensbi mailing list opensbi@lists.infradead.org http://lists.infradead.org/mailman/listinfo/opensbi --===============6698134897843493998==--