On Mon, Aug 31, 2026 at 10:07 PM +0200, Valentin Haudiquet wrote:
> De-vote power-down for all four clusters and the boot hart's core
> BEFORE enabling CCI.  Also deassert DMASYS reset and enable its clock
> before CCI: the DMA engine sits behind the AIDMA CCI slave interface,
> and if DMASYS is held in reset the CCI busy-wait hangs when enabling
> snoop/DVM on that interface.
>
> @@ -88,10 +113,21 @@ static void spacemit_k3_pre_init(void)
>  	writel((u32)entry, (void *)(unsigned long)C3_RVBADDR_LO_ADDR);
>  	writel((u32)(entry >> 32), (void *)(unsigned long)C3_RVBADDR_HI_ADDR);
>  
> +	/* De-vote all cluster power-downs BEFORE CCI enable. */
> +	spacemit_k3_keep_all_clusters_powered();
> +	spacemit_k3_keep_boot_hart_powered();
> +
> +	/*
> +	 * Deassert DMASYS reset and enable its clock before CCI: the DMA
> +	 * engine sits behind the AIDMA CCI slave interface.  If DMASYS is
> +	 * held in reset or its clock is gated, the CCI busy-wait hangs when
> +	 * enabling snoop/DVM on that interface.
> +	 */
> +	writel(DMASYS_RESET_DEASSERT, (void *)(unsigned long)DMASYS_RESET);
> +	writel(DMASYS_CLK_EN_BIT, (void *)(unsigned long)DMASYS_CLK_EN);
> +
>  	for (i = 0; i < array_size(cci_map); i++)
>  		cci_enable_snoop_dvm_reqs(cci_map, i);
> -
> -	spacemit_k3_keep_boot_hart_powered();

This ordering does not match the vendor OpenSBI implementation we have. It
enables CCI interfaces 0 through 6 before de-voting the cluster power-down
bits, and ungates DMASYS only after CCI setup.

Which slave interface remains change-pending, and what register state did
you observe before these writes? Please also specify the boot firmware and
DT combination used for the test. Since cluster de-voting and DMASYS
ungating are independent changes, they should be tested and justified
separately.

The patch also leaves every cluster de-voted after CCI setup. Is that
required, or should the previous power-down state be restored?

                                            - Troy