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From: Ved Shanbhogue <ved@rivosinc.com>
To: opensbi@lists.infradead.org
Subject: [RISC-V] [tech-unixplatformspec] SBI Debug Console Extension Proposal (Draft v2)
Date: Mon, 27 Jun 2022 08:52:42 -0500	[thread overview]
Message-ID: <Yrm2KomP8IdT5Co3@ved-XPS-8940> (raw)
In-Reply-To: <CAK9=C2WEYHEo-5i6dNkxT=8owD98UHx-wJtb_oFwu-95=Pee5Q@mail.gmail.com>

On Mon, Jun 27, 2022 at 06:58:15PM +0530, Anup Patel wrote:
>
>The rationale is that for M-mode the memory type is always defined by
>PMA(s) so if supervisor-mode software overrides memory type using
>Svpbmt then M-mode firmware will not see same contents as the
>supervisor-mode software.

I get the intent now. But we may not want to prohibit that.

We may want to document that the SBI will access this memory using
the PMA attribute. 

If the supervisor has accessed this same location using different 
cachability attribute than the PMA then a loss of coherence or 
unexpected memory ordering may occur and the invoking software 
should follow the rules and sequences defined in the Svpbmt 
specification to prevent the loss of coherence and memory ordering.

This does not place a restriction but warns against the issue and
points to the right sequence if there is a legitimate reason to 
do it.

This should not be specific to this function but applicable to any
function that the SBI defines with a memory operand and so could be
stated more generally in the SBI specification.

regards
ved


      reply	other threads:[~2022-06-27 13:52 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-27  8:46 SBI Debug Console Extension Proposal (Draft v2) Anup Patel
2022-06-27 11:15 ` [RISC-V] [tech-unixplatformspec] " Heinrich Schuchardt
2022-06-27 12:08   ` Anup Patel
2022-06-27 12:40     ` Heinrich Schuchardt
2022-06-27 12:46     ` Ved Shanbhogue
2022-06-27 13:28       ` Anup Patel
2022-06-27 13:52         ` Ved Shanbhogue [this message]

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