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From: Yu-Chien Peter Lin <peterlin@andestech.com>
To: opensbi@lists.infradead.org
Subject: [PATCH v3 04/15] sbi: sbi_pmu: Add hw_counter_filter_mode() to pmu device
Date: Tue, 28 Nov 2023 14:10:14 +0800	[thread overview]
Message-ID: <ZWWERnFB6qoX6XQg@APC323> (raw)
In-Reply-To: <CAOnJCUK4_H=MeHsUUCDscVD+905k6uV9C3bUUpwuA+kTdsFYUw@mail.gmail.com>

Hi Atish,

On Wed, Nov 22, 2023 at 04:24:35PM -0800, Atish Patra wrote:
> On Tue, Nov 21, 2023 at 11:40?PM Yu Chien Peter Lin
> <peterlin@andestech.com> wrote:
> >
> > Add support for custom PMU extensions to set inhibit bits
> > on custom CSRs by introducing the PMU device callback
> > hw_counter_filter_mode(). This allows the perf tool to
> > restrict event counting under a specified privileged
> > mode by appending a modifier, e.g. perf record -e event:k
> > to count events only happening in kernel mode.
> >
> > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> > Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
> > ---
> > Changes v1 -> v2:
> >   - No change
> > Changes v2 -> v3:
> >   - Add pmu_dev->hw_counter_filter_mode() in pmu_fixed_ctr_update_inhibit_bits()
> > ---
> >  include/sbi/sbi_pmu.h |  6 ++++++
> >  lib/sbi/sbi_pmu.c     | 20 ++++++++++++++------
> >  2 files changed, 20 insertions(+), 6 deletions(-)
> >
> > diff --git a/include/sbi/sbi_pmu.h b/include/sbi/sbi_pmu.h
> > index 16f6877..d63149c 100644
> > --- a/include/sbi/sbi_pmu.h
> > +++ b/include/sbi/sbi_pmu.h
> > @@ -89,6 +89,12 @@ struct sbi_pmu_device {
> >          * Custom function returning the machine-specific irq-bit.
> >          */
> >         int (*hw_counter_irq_bit)(void);
> > +
> > +       /**
> > +        * Custom function to inhibit counting of events while in
> > +        * specified mode.
> > +        */
> > +       void (*hw_counter_filter_mode)(unsigned long flags, int counter_index);
> >  };
> >
> >  /** Get the PMU platform device */
> > diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c
> > index 3cbd4ff..2f255de 100644
> > --- a/lib/sbi/sbi_pmu.c
> > +++ b/lib/sbi/sbi_pmu.c
> > @@ -599,7 +599,10 @@ static int pmu_update_hw_mhpmevent(struct sbi_pmu_hw_event *hw_evt, int ctr_idx,
> >                 pmu_dev->hw_counter_disable_irq(ctr_idx);
> >
> >         /* Update the inhibit flags based on inhibit flags received from supervisor */
> > -       pmu_update_inhibit_flags(flags, &mhpmevent_val);
> > +       if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSCOFPMF))
> > +               pmu_update_inhibit_flags(flags, &mhpmevent_val);
> > +       if (pmu_dev && pmu_dev->hw_counter_filter_mode)
> > +               pmu_dev->hw_counter_filter_mode(flags, ctr_idx);
> >
> >  #if __riscv_xlen == 32
> >         csr_write_num(CSR_MHPMEVENT3 + ctr_idx - 3, mhpmevent_val & 0xFFFFFFFF);
> > @@ -620,7 +623,8 @@ static int pmu_fixed_ctr_update_inhibit_bits(int fixed_ctr, unsigned long flags)
> >  #if __riscv_xlen == 32
> >         uint64_t cfgh_csr_no;
> >  #endif
> > -       if (!sbi_hart_has_extension(scratch, SBI_HART_EXT_SMCNTRPMF))
> > +       if (!sbi_hart_has_extension(scratch, SBI_HART_EXT_SMCNTRPMF) &&
> > +               !sbi_hart_has_extension(scratch, SBI_HART_EXT_XANDESPMU))
> 
> Instead of adding a check for vendor extension, we can just check for
> platform specific hw_counter_filter_mode() availability.

Sure, will do.

Regards,
Peter Lin

> I would prefer to avoid any vendor specific code if possible. Ideally,
> all vendor specific details should be abstracted out via pmu-dev.
> 
> >                 return fixed_ctr;
> >
> >         switch (fixed_ctr) {
> > @@ -641,13 +645,17 @@ static int pmu_fixed_ctr_update_inhibit_bits(int fixed_ctr, unsigned long flags)
> >         }
> >
> >         cfg_val |= MHPMEVENT_MINH;
> > -       pmu_update_inhibit_flags(flags, &cfg_val);
> > +       if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SMCNTRPMF)) {
> > +               pmu_update_inhibit_flags(flags, &cfg_val);
> >  #if __riscv_xlen == 32
> > -       csr_write_num(cfg_csr_no, cfg_val & 0xFFFFFFFF);
> > -       csr_write_num(cfgh_csr_no, cfg_val >> BITS_PER_LONG);
> > +               csr_write_num(cfg_csr_no, cfg_val & 0xFFFFFFFF);
> > +               csr_write_num(cfgh_csr_no, cfg_val >> BITS_PER_LONG);
> >  #else
> > -       csr_write_num(cfg_csr_no, cfg_val);
> > +               csr_write_num(cfg_csr_no, cfg_val);
> >  #endif
> > +       }
> > +       if (pmu_dev && pmu_dev->hw_counter_filter_mode)
> > +               pmu_dev->hw_counter_filter_mode(flags, fixed_ctr);
> >         return fixed_ctr;
> >  }
> >
> > --
> > 2.34.1
> >
> 
> 
> --
> Regards,
> Atish


  reply	other threads:[~2023-11-28  6:10 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-22  7:36 [PATCH v3 00/15] Add Andes PMU extension support Yu Chien Peter Lin
2023-11-22  7:36 ` [PATCH v3 01/15] lib: ipi: Adjust Andes PLICSW to single-bit-per-hart scheme Yu Chien Peter Lin
2023-11-24 14:43   ` Lad, Prabhakar
2023-11-22  7:36 ` [PATCH v3 02/15] sbi: sbi_pmu: Improve sbi_pmu_init() error handling Yu Chien Peter Lin
2023-11-22 23:47   ` Atish Patra
2023-11-28  5:33     ` Yu-Chien Peter Lin
2023-11-24 14:45   ` Lad, Prabhakar
2023-11-22  7:36 ` [PATCH v3 03/15] lib: sbi: Add Xandespmu in hart extensions Yu Chien Peter Lin
2023-11-23  0:02   ` Atish Patra
2023-11-24 14:45   ` Lad, Prabhakar
2023-11-22  7:36 ` [PATCH v3 04/15] sbi: sbi_pmu: Add hw_counter_filter_mode() to pmu device Yu Chien Peter Lin
2023-11-23  0:24   ` Atish Patra
2023-11-28  6:10     ` Yu-Chien Peter Lin [this message]
2023-11-22  7:36 ` [PATCH v3 05/15] platform: include: andes45: Add PMU related CSR defines Yu Chien Peter Lin
2023-11-23 16:53   ` Atish Patra
2023-11-24 14:47   ` Lad, Prabhakar
2023-11-22  7:36 ` [PATCH v3 06/15] platform: generic: Introduce pmu_init() platform override Yu Chien Peter Lin
2023-11-23  0:25   ` Atish Patra
2023-11-24 14:49   ` Lad, Prabhakar
2023-11-22  7:36 ` [PATCH v3 07/15] platform: andes: Add Andes custom PMU support Yu Chien Peter Lin
2023-11-23  2:24   ` Samuel Holland
2023-11-28 11:02     ` Yu-Chien Peter Lin
2023-11-22  7:36 ` [PATCH v3 08/15] platform: andes: Enable Andes PMU for AE350 Yu Chien Peter Lin
2023-11-23 16:55   ` Atish Patra
2023-11-24 14:52   ` Lad, Prabhakar
2023-11-22  7:36 ` [PATCH v3 09/15] platform: rzfive: Enable Andes PMU for RZ/Five Yu Chien Peter Lin
2023-11-23 16:56   ` Atish Patra
2023-11-24 14:53   ` Lad, Prabhakar
2023-11-22  7:36 ` [PATCH v3 10/15] lib: utils: fdt_fixup: Allow preserving PMU properties Yu Chien Peter Lin
2023-11-22 23:41   ` Atish Patra
2023-11-24 14:54   ` Lad, Prabhakar
2023-11-25  4:42   ` Anup Patel
2023-11-28  9:57     ` Yu-Chien Peter Lin
2023-11-22  7:36 ` [PATCH v3 11/15] platform: andes: Factor out is_andes() helper Yu Chien Peter Lin
2023-11-22  7:36 ` [PATCH v3 12/15] lib: utils: fdt_pmu: Make the fdt_pmu_evt_select table global variable Yu Chien Peter Lin
2023-11-22  7:36 ` [PATCH v3 13/15] lib: utils: fdt_pmu: Do not iterate over the fdt_pmu_evt_select table Yu Chien Peter Lin
2023-11-22  7:36 ` [PATCH v3 14/15] platform: andes: Add Andes default PMU mapping support Yu Chien Peter Lin
2023-11-24 14:55   ` Lad, Prabhakar
2023-11-22  7:36 ` [PATCH v3 15/15] docs: pmu: Add Andes PMU node example Yu Chien Peter Lin
2023-11-24 14:56   ` Lad, Prabhakar
2023-11-23  0:07 ` [PATCH v3 00/15] Add Andes PMU extension support Atish Patra
2023-11-23  0:27   ` Atish Patra
2023-11-28  5:23     ` Yu-Chien Peter Lin

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