Re: TH1520: broken CPU count detection

[Yao Zi <me@ziyao.cc>]

On Thu, Sep 17, 2026 at 12:54:49PM +0200, Michael Opdenacker wrote:
> Hi Yao
> 
> On 9/16/26 6:42 PM, Yao Zi wrote:
> > On Tue, Sep 15, 2026 at 09:31:01AM +0200, Michael Opdenacker wrote:
> > > Greetings,
> > > 
> > > For the Yocto meta-riscv layer, we're trying to replace the downstream
> > > opensbi (called opensbi-revyos) by mainline opensbi:
> > > https://github.com/riscv/meta-riscv/pull/685/
> > > 
> > > The board boots fine, but unfortunately, only 1 CPU core is detected. This
> > > surfaces in the Linux kernel log:
> > > 
> > > [    0.089851] smp: Bringing up secondary CPUs ...
> > > [   10.165542] CPU1 failed to report alive state
> > > [   20.241632] CPU2 failed to report alive state
> > > [   30.316980] CPU3 failed to report alive state
> > What Linux kernel are you using?
> I'm using mainline Linux 7.2.x.
> Is this something Linux can manage?

Okay, I guess I should have more sleep when writing this reply. I was
meant to ask the U-Boot you're using.

The problem is that, mainline OpenSBI doesn't have the ability to bring
CPU cores out of reset, while T-Head's original vendor U-Boot doesn't,
either, and relies on OpenSBI to do the stuff (iirc through a devicetree
node called "reset-sample" or similar).

So if you're working with T-Head's original U-Boot but with mainline
OpenSBI, then there's no one bringing secondary cores up.

RevyOS' fork of T-Head's U-Boot[1] implements bringing up logic, too, so
it works with mainline OpenSBI. So does mainline U-Boot.

> Thanks
> Michael

[1]: https://github.com/revyos/th1520-vendor-uboot/blob/th1520/arch/riscv/lib/bootm.c

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