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Tue, 29 Sep 2026 07:29:46 -0700 (PDT) Received: from plin-1878 ([136.226.240.195]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3a497f1b13esm6129428a91.9.2026.09.29.07.29.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Sep 2026 07:29:44 -0700 (PDT) Date: Tue, 29 Sep 2026 22:29:38 +0800 From: Yu-Chien Peter Lin To: Krzysztof Kozlowski Cc: opensbi@lists.infradead.org, zong.li@sifive.com, greentime.hu@sifive.com, anup@brainfault.org, scott@riscstar.com, conor@kernel.org, dave.patel@riscstar.com, raymond.mao@riscstar.com, robin.randhawa@sifive.com, samuel.holland@sifive.com, pawandeep.oza@oss.qualcomm.com Subject: Re: [PATCH v2 0/9] Add RISC-V Worlds ISA support to OpenSBI Message-ID: References: <20260817090503.2104998-1-peter.lin@sifive.com> <43ee673a-8df0-4b6f-9e8d-eeda05eb32b9@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <43ee673a-8df0-4b6f-9e8d-eeda05eb32b9@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260929_152948_825572_A9D371E8 X-CRM114-Status: GOOD ( 22.65 ) X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "opensbi" Errors-To: opensbi-bounces+opensbi=archiver.kernel.org@lists.infradead.org Hi Krzysztof, On Mon, Sep 28, 2026 at 01:33:17PM +0200, Krzysztof Kozlowski wrote: > On 17/08/2026 11:04, Yu-Chien Peter Lin wrote: > > This patch series adds support for RISC-V Worlds ISA extensions, > > enabling hardware-enforced isolation boundaries based on World IDs > > by extending the OpenSBI domain framework. > > > > Trust Model and Boot-time Roles > > -------------------------------- > > > > The implementation follows the two-phase M-mode trust model: > > > > - RoT M-mode phase: Prior boot stage (ROM/SPL) that may program mwid and > > mlwidlist and lock mwid before handing off to OpenSBI. > > > > - Regular M-mode phase (OpenSBI): Treats pmwid/pmwidlist/pmlwidlist as > > input policy from hardware/RoT. Locks mwid to prevent later M-mode code > > from changing its own WID. Programs per-domain mlwid/mwiddeleg based on > > DT configuration. > > > > Device Tree Bindings > > --------------------- > > > > Per-hart properties defined in linux kernel DT bindings v3 [1]: > > - riscv,pmwid: M-mode World ID > > - riscv,pmwidlist: M-mode permitted WID bitmap > > - riscv,pmlwidlist: S/U-mode permitted WID bitmap> > > Per-domain properties (see domain_support.md): > > - wid: S-mode WID for this domain > > - widdeleg: WID delegation bitmap for this domain > > > I don't understand why I am cc-ed here, OpenSBI consumes the riscv,pmwid/pmwidlist/pmlwidlist properties. Sorry for the confusion; I will remove you from the CC list and provide links to the associated OpenSBI patches in the kernel patch cover letter. > why DT is described here but not > in the bindings and why do you reference some RFC (which means: not > READY for review) patchset in a different patchset which is ready for > review. The kernel patch series is currently pending and cannot be merged until the RISC-V Worlds specification has landed with an associated commit hash. Therefore, I used a TBD placeholder in PATCH 2 [1]. Best regards, Peter Lin [1] https://patchwork.kernel.org/project/linux-riscv/patch/20260812122131.1534906-2-peter.lin@sifive.com/ > > Best regards, > Krzysztof -- opensbi mailing list opensbi@lists.infradead.org http://lists.infradead.org/mailman/listinfo/opensbi