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[106.167.137.155]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-35dbe5e5127sm1088235a91.1.2026.03.31.00.57.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 31 Mar 2026 00:57:50 -0700 (PDT) Message-ID: <02bc543c-48c6-401f-8a61-59090c50e490@gmail.com> Date: Tue, 31 Mar 2026 16:57:49 +0900 Precedence: bulk X-Mailing-List: perfbook@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH -perfbook 2/3] cpu/overview: Tweak index markings To: "Paul E. McKenney" Cc: perfbook@vger.kernel.org, Akira Yokosawa References: <7304a7e5-2b6d-4109-9387-01fa4015cbf0@gmail.com> Content-Language: en-US From: Akira Yokosawa In-Reply-To: <7304a7e5-2b6d-4109-9387-01fa4015cbf0@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Let's make them more consistent with other index markings. Signed-off-by: Akira Yokosawa --- cpu/overview.tex | 4 ++-- glossary.tex | 14 ++++++-------- indexsee.tex | 1 + 3 files changed, 9 insertions(+), 10 deletions(-) diff --git a/cpu/overview.tex b/cpu/overview.tex index 56c843ef..4a3ac25a 100644 --- a/cpu/overview.tex +++ b/cpu/overview.tex @@ -456,14 +456,14 @@ But here in 2026, such computers are the exception rather than the rule. In fact, most computers exist only to respond to requests transmitted to them from all over the world. These requests are received by devices within the computers system, -and then these devices \emph{\IX{interrupt}} a CPU to inform it that +and then these devices \emph{\IXB{interrupt}} a CPU to inform it that a new request has arrived. A CPU must also transmit responses via these same devices, which in turn might interrupt the CPU when a given transmission has completed. CPUs can also interrupt each other using \IXacrfpl{ipi}. Either way, the CPU disables further interrupts, commences executing an -\emph{\IXG{interrupt handler}}, and once this handler has completed, +\emph{\IXB{interrupt handler}}, and once this handler has completed, the CPU re-enables interrupts and resumes executing whatever sequence of instructions was interrupted. These interrupts take time away from whatever task the CPU was executing, diff --git a/glossary.tex b/glossary.tex index f65f4dff..628e5724 100644 --- a/glossary.tex +++ b/glossary.tex @@ -368,9 +368,11 @@ CPUs are available). \item[\IXG{Immutable}:] In this book, a synonym for read-mostly. -\item[\IXG{Inter-Processor Interrupt}:]\glsuseriii{ipi} +\item[Inter-Processor Interrupt (IPI):]\glsuseriii{ipi} An interrupt sent by a CPU instead of by an I/O device. - See IPI. + IPIs are used heavily in the Linux kernel, for example, within + the scheduler to alert CPUs that a high-priority process is now + runnable. \item[\IXG{Interrupt}:] A signal to a CPU that causes it to stop whatever it is doing, disable interrupts, and execute an interrupt handler. @@ -387,12 +389,8 @@ If necessary, the item is removed from the other CPUs' caches via ``invalidation'' messages from the writing CPUs to any CPUs having a copy in their caches. -\item[IPI:]\glsuseriii{ipi} - Inter-processor interrupt, which is an - interrupt sent from one CPU to another. - IPIs are used heavily in the Linux kernel, for example, within - the scheduler to alert CPUs that a high-priority process is now - runnable. +\item[IPI:] + See ``Inter-Processor Interrupt (IPI)''. \item[IRQ:]\glsuseriii{irq} Interrupt request, often used as an abbreviation for ``interrupt'' within the Linux kernel community, as in ``irq handler''. diff --git a/indexsee.tex b/indexsee.tex index fe57094b..cad3532f 100644 --- a/indexsee.tex +++ b/indexsee.tex @@ -1,6 +1,7 @@ % effective in both single- and two- level index \index{Coherence|see{Cache coherence}} \index{Full(y) multi-copy atomic|see{Multi-copy atomic}} +\index{IPI|see{Inter-processor interrupt}} \index{Memory consistency model|see{Memory model}} \index{Single-copy atomic|see{Cache coherence}} \index{Single-variable SC|see{Cache coherence}} -- 2.43.0