Re: [PATCH] advsync: Fix control-dependency no-transitivity example

["Paul E. McKenney" <paulmck@linux.vnet.ibm.com>]

On Fri, Jul 14, 2017 at 11:34:45PM +0900, Akira Yokosawa wrote:
> >From 8740c546fbb6988c2fcf4a88c4314df972d0b9b7 Mon Sep 17 00:00:00 2001
> From: Akira Yokosawa <akiyks@gmail.com>
> Date: Fri, 14 Jul 2017 22:48:37 +0900
> Subject: [PATCH] advsync: Fix control-dependency no-transitivity example
> 
> The corresponding assert condition in memory-barriers.txt was
> fixed in commit 5646f7acc95f ("memory-barriers: Fix control-
> ordering no-transitivity example") of Linux kernel repository.
> Somehow it was imported to perfbook in a wrong form and has
> survived since.
> 
> Signed-off-by: Akira Yokosawa <akiyks@gmail.com>

And I did take this, thank you very much, and please accept my apologies
for the delay.

If I understand correctly, I should leave your second patch alone.
If I am confused, please let me know!

							Thanx, Paul

> ---
>  advsync/memorybarriers.tex | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/advsync/memorybarriers.tex b/advsync/memorybarriers.tex
> index c9c975c..25a90b2 100644
> --- a/advsync/memorybarriers.tex
> +++ b/advsync/memorybarriers.tex
> @@ -3036,9 +3036,9 @@ not), then adding the following CPU would guarantee a related assertion:
>  \begin{tabular}{l}
>  	\nf{CPU 2} \\
>  	\hline
> -	\tco{WRITE_ONCE(y, 1);} \\
> +	\tco{WRITE_ONCE(x, 2);} \\
>  	\multicolumn{1}{l}{~} \\
> -	\multicolumn{1}{l}{\tco{assert(!(r1 == 1 && r2 == 1 && x == 1));}} \\
> +	\multicolumn{1}{l}{\tco{assert(!(r1 == 2 && r2 == 1 && x == 2));}} \\
>  \end{tabular}
>  \end{minipage}
>  \vspace{5pt}
> -- 
> 2.7.4
>