From: "Paul E. McKenney" <paulmck@linux.ibm.com>
To: Elad Lahav <e2lahav@gmail.com>
Cc: perfbook@vger.kernel.org
Subject: Re: Cost of atomic operations on new hardware
Date: Sat, 27 Apr 2019 10:45:34 -0700 [thread overview]
Message-ID: <20190427174534.GS3923@linux.ibm.com> (raw)
In-Reply-To: <CAJbg=FWZhjXARBNou6XZ55fdvRsgABR19p8pytYB+SrKFtwWxQ@mail.gmail.com>
On Fri, Apr 26, 2019 at 07:06:10AM -0400, Elad Lahav wrote:
> Hello,
>
> Section 3.1.3 contains the following statement:
>
> "Fortunately, CPU designers have focused heavily on atomic operations,
> so that as of early 2014 they have greatly reduced their overhead."
>
> My experience with very recent hardware is that the *relative* cost of
> atomic operations has actually increased significantly. It seems that
> hardware designers, in their attempt to optimize performance for
> certain workloads, have produced hardware in which the "anomalous"
> conditions (atomic operations, cache misses, barriers, exceptions)
> incur much higher penalties than in the past. I assume that this is
> primarily the result of more intensive speculation and prediction.
Some of the early 2000s systems had -really- atomic operations, but I
have not kept close track since 2014.
How would you suggest that this be measured? Do you have access to
a range of hardweare that would permit us to include something more
definite and measurable?
Thanx, Paul
next prev parent reply other threads:[~2019-04-27 17:45 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-26 11:06 Cost of atomic operations on new hardware Elad Lahav
2019-04-27 17:45 ` Paul E. McKenney [this message]
2019-04-27 20:24 ` Elad Lahav
2019-04-28 6:11 ` Paul E. McKenney
2019-04-29 10:51 ` Elad Lahav
2019-05-12 20:52 ` Paul E. McKenney
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