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X-CSE-ConnectionGUID: a5wRy4p+TVe1K6h99VPE6g== X-CSE-MsgGUID: H9OWlJgHQvSe4jlCCsRRdw== X-IronPort-AV: E=McAfee;i="6800,10657,11810"; a="107081900" X-IronPort-AV: E=Sophos;i="6.24,194,1774335600"; d="scan'208";a="107081900" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jun 2026 02:18:47 -0700 X-CSE-ConnectionGUID: yqbXB29sQVmXBJOwAzbegw== X-CSE-MsgGUID: XkQsdjnwQumLP+KsyKW2WA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,194,1774335600"; d="scan'208";a="275693406" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.244.182]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jun 2026 02:18:44 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Date: Mon, 8 Jun 2026 12:18:40 +0300 (EEST) To: Shyam Sundar S K cc: Hans de Goede , platform-driver-x86@vger.kernel.org, mario.limonciello@amd.com, Sanket.Goswami@amd.com Subject: Re: [PATCH v2 2/2] platform/x86/amd/pmc: Add PMC driver support for AMD 1Ah M80H SoC In-Reply-To: <20260601112103.1690951-3-Shyam-sundar.S-k@amd.com> Message-ID: <13db00fa-ec6b-4de7-d5ec-c9d9895af7d4@linux.intel.com> References: <20260601112103.1690951-1-Shyam-sundar.S-k@amd.com> <20260601112103.1690951-3-Shyam-sundar.S-k@amd.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII On Mon, 1 Jun 2026, Shyam Sundar S K wrote: > The 1Ah M80H SoC uses a different set of SMU mailbox register offsets > compared to the existing 1Ah variants: message at 0xA10, argument at > 0xA18, and response at 0xA14. > > Add amd_1ah_m80_cpu_info with these offsets, wire it into the PCI ID > table via PCI_DEVICE_DATA(), handle it in amd_pmc_set_cpu_info() and > amd_pmc_idlemask_read(), and add the corresponding ACPI ID AMDI000C. > > Co-developed-by: Sanket Goswami > Signed-off-by: Sanket Goswami > Signed-off-by: Shyam Sundar S K > --- > drivers/platform/x86/amd/pmc/pmc.c | 15 +++++++++++++++ > drivers/platform/x86/amd/pmc/pmc.h | 6 ++++++ > 2 files changed, 21 insertions(+) > > diff --git a/drivers/platform/x86/amd/pmc/pmc.c b/drivers/platform/x86/amd/pmc/pmc.c > index 6c7fa80c7f09..8da988016661 100644 > --- a/drivers/platform/x86/amd/pmc/pmc.c > +++ b/drivers/platform/x86/amd/pmc/pmc.c > @@ -131,6 +131,15 @@ static const struct amd_pmc_cpu_info amd_1ah_m70_cpu_info = { > .os_hint = MSG_OS_HINT_RN, > }; > > +static const struct amd_pmc_cpu_info amd_1ah_m80_cpu_info = { > + .smu_msg = AMD_PMC_REGISTER_MSG_1AH_80H, > + .smu_arg = AMD_PMC_REGISTER_ARG_1AH_80H, > + .smu_rsp = AMD_PMC_REGISTER_RSP_1AH_80H, > + .num_ips = ARRAY_SIZE(soc15_ip_blk), > + .ips_ptr = soc15_ip_blk, > + .os_hint = MSG_OS_HINT_RN, > +}; > + > static bool disable_workarounds; > module_param(disable_workarounds, bool, 0644); > MODULE_PARM_DESC(disable_workarounds, "Disable workarounds for platform bugs"); > @@ -172,6 +181,9 @@ static void amd_pmc_set_cpu_info(struct amd_pmc_dev *dev) > else > info = &amd_1ah_cpu_info; > break; > + case PCI_DEVICE_ID_AMD_1AH_M80H_ROOT: > + info = &amd_1ah_m80_cpu_info; This shouldn't be necessary if you get it directly from the match. > + break; > default: > dev_err(dev->dev, "Unknown CPU ID: 0x%x\n", dev->cpu_id); > return; > @@ -415,6 +427,7 @@ static int amd_pmc_idlemask_read(struct amd_pmc_dev *pdev, struct device *dev, > break; > case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT: > case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT: > + case PCI_DEVICE_ID_AMD_1AH_M80H_ROOT: > val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_1AH); I guess the scratch register too could come from the info, you just need to handle the AMD_CPU_ID_CZN version check prior to that. I really like how clean adding new platforms becomes with the info infrastructure in place. Thanks. > break; > default: > @@ -763,6 +776,7 @@ static const struct pci_device_id pmc_pci_ids[] = { > { PCI_DEVICE_DATA(AMD, CPU_ID_SHP, NULL) }, > { PCI_DEVICE_DATA(AMD, 1AH_M20H_ROOT, NULL) }, > { PCI_DEVICE_DATA(AMD, 1AH_M60H_ROOT, NULL) }, > + { PCI_DEVICE_DATA(AMD, 1AH_M80H_ROOT, &amd_1ah_m80_cpu_info) }, > { } > }; > > @@ -882,6 +896,7 @@ static const struct acpi_device_id amd_pmc_acpi_ids[] = { > {"AMDI0009", 0}, > {"AMDI000A", 0}, > {"AMDI000B", 0}, > + {"AMDI000C", 0}, > {"AMD0004", 0}, > {"AMD0005", 0}, > { } > diff --git a/drivers/platform/x86/amd/pmc/pmc.h b/drivers/platform/x86/amd/pmc/pmc.h > index 0fd0ced21831..0a3b81944920 100644 > --- a/drivers/platform/x86/amd/pmc/pmc.h > +++ b/drivers/platform/x86/amd/pmc/pmc.h > @@ -22,6 +22,11 @@ > /* SMU communication registers for 1Ah 20h SoC */ > #define AMD_PMC_REGISTER_MSG_1AH_20H 0x938 > > +/* SMU communication registers for 1Ah 80h SoC */ > +#define AMD_PMC_REGISTER_MSG_1AH_80H 0xA10 > +#define AMD_PMC_REGISTER_ARG_1AH_80H 0xA18 > +#define AMD_PMC_REGISTER_RSP_1AH_80H 0xA14 > + > /* PMC Scratch Registers */ > #define AMD_PMC_SCRATCH_REG_CZN 0x94 > #define AMD_PMC_SCRATCH_REG_YC 0xD14 > @@ -189,6 +194,7 @@ void amd_mp2_stb_deinit(struct amd_pmc_dev *dev); > > #define PCI_DEVICE_ID_AMD_1AH_M20H_ROOT 0x1507 > #define PCI_DEVICE_ID_AMD_1AH_M60H_ROOT 0x1122 > +#define PCI_DEVICE_ID_AMD_1AH_M80H_ROOT 0x115b > #define PCI_DEVICE_ID_AMD_MP2_STB 0x172c > > int amd_stb_s2d_init(struct amd_pmc_dev *dev); > -- i.