On Wed, 6 Nov 2024, Basavaraj Natikar wrote: > Add documentation for the amd_3d_vcache sysfs bus platform driver > interface so that userspace applications can use it to change mode > preferences, either frequency or cache. > > Co-developed-by: Perry Yuan > Signed-off-by: Perry Yuan > Co-developed-by: Mario Limonciello > Signed-off-by: Mario Limonciello > Reviewed-by: Shyam Sundar S K > Reviewed-by: Armin Wolf > Signed-off-by: Basavaraj Natikar > --- > .../sysfs-bus-platform-drivers-amd_x3d_vcache | 12 ++++++++++++ > MAINTAINERS | 1 + > 2 files changed, 13 insertions(+) > create mode 100644 Documentation/ABI/testing/sysfs-bus-platform-drivers-amd_x3d_vcache > > diff --git a/Documentation/ABI/testing/sysfs-bus-platform-drivers-amd_x3d_vcache b/Documentation/ABI/testing/sysfs-bus-platform-drivers-amd_x3d_vcache > new file mode 100644 > index 000000000000..5ff1f1a8c9b6 > --- /dev/null > +++ b/Documentation/ABI/testing/sysfs-bus-platform-drivers-amd_x3d_vcache > @@ -0,0 +1,12 @@ > +What: /sys/bus/platform/drivers/amd_x3d_vcache/AMDI0101:00/amd_x3d_mode > +Date: October 2024 Space -> tabs. With that addressed, Reviewed-by: Ilpo Järvinen > +KernelVersion: 6.13 > +Contact: Basavaraj Natikar > +Description: (RW) AMD 3D V-Cache optimizer allows users to switch CPU core > + rankings dynamically. > + > + This file switches between these two modes: > + - "frequency" cores within the faster CCD are prioritized before > + those in the slower CCD. > + - "cache" cores within the larger L3 CCD are prioritized before > + those in the smaller L3 CCD. > diff --git a/MAINTAINERS b/MAINTAINERS > index 60155effead9..5c29cdc6c1a4 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -970,6 +970,7 @@ M: Basavaraj Natikar > R: Mario Limonciello > L: platform-driver-x86@vger.kernel.org > S: Supported > +F: Documentation/ABI/testing/sysfs-bus-platform-drivers-amd_x3d_vcache > F: drivers/platform/x86/amd/x3d_vcache.c > > AMD ADDRESS TRANSLATION LIBRARY (ATL) > -- i.