From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jarkko Sakkinen Subject: [PATCH v15 04/23] x86/msr: Add IA32_FEATURE_CONTROL.SGX_ENABLE definition Date: Sat, 3 Nov 2018 01:11:03 +0200 Message-ID: <20181102231320.29164-5-jarkko.sakkinen@linux.intel.com> References: <20181102231320.29164-1-jarkko.sakkinen@linux.intel.com> Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Return-path: In-Reply-To: <20181102231320.29164-1-jarkko.sakkinen@linux.intel.com> Sender: linux-kernel-owner@vger.kernel.org To: x86@kernel.org, platform-driver-x86@vger.kernel.org, linux-sgx@vger.kernel.org Cc: dave.hansen@intel.com, sean.j.christopherson@intel.com, nhorman@redhat.com, npmccallum@redhat.com, serge.ayoun@intel.com, shay.katz-zamir@intel.com, haitao.huang@intel.com, mark.shanahan@intel.com, andriy.shevchenko@linux.intel.com, Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , Jarkko Sakkinen , Konrad Rzeszutek Wilk , Tom Lendacky , Paolo Bonzini , Matt Turner , Janakarajan Natarajan , David Woodhouse , "open list:X86 ARCHITECTURE 32-BIT AND 64-BIT" List-Id: platform-driver-x86.vger.kernel.org From: Sean Christopherson Add a new IA32_FEATURE_CONTROL bit, SGX_ENABLE, which must be set in order to execute SGX instructions, i.e. ENCL{S,U,V}. The existence of the bit is enumerated by CPUID as X86_FEATURE_SGX. Like all other flags in IA32_FEATURE_CONTROL, the MSR must be locked for SGX_ENABLE to take effect. Signed-off-by: Sean Christopherson --- arch/x86/include/asm/msr-index.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 4731f0cf97c5..2837f65ac817 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -486,6 +486,7 @@ #define FEATURE_CONTROL_LOCKED (1<<0) #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) +#define FEATURE_CONTROL_SGX_ENABLE (1<<18) #define FEATURE_CONTROL_LMCE (1<<20) #define MSR_IA32_APICBASE 0x0000001b -- 2.19.1