From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B20550EC0D for ; Thu, 3 Sep 2026 20:11:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.17 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788466277; cv=none; b=fElp/6vQpNtQEN3mq5zwZOhzO/fZbzKTIVF685g9sYpKaueDME2AbdeTNlS2gY/z2eti7SNLCAxqsGqIswOy5WCIiDapScCK3fFvZjbV0lRq/HJc2smh2wA1sFU+80rYTRp6xbU+j3S7uRBDHZ+HKzvb0ZkmHJuWGK9RXjRWenE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788466277; c=relaxed/simple; bh=dJ23TjJwGFqAUHr7Ar4X9qnZRf9dv9fdIiDiNuk2Zqc=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mLmAhqm7I0WJum0dScuC44gPQ4qp7ot61FOTI9xT3ijeaR5bgdQi4KNJlYYLt0iULsaWVsRNiSHUXH5yKeJQM50ZCz7HNMozUJbeB+OfEsmU6qN+0t1cE6hcwdlp5tcxg5P0AXEpn8H47vx92oOMtY7KNKz+2LadU0Gi2lnT0WQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=nR7bNdKp; arc=none smtp.client-ip=198.175.65.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="nR7bNdKp" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1788466271; x=1820002271; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=dJ23TjJwGFqAUHr7Ar4X9qnZRf9dv9fdIiDiNuk2Zqc=; b=nR7bNdKpXRm47IrBGOLMp5VsOrzKEBrCgecRb+Tv54YW3b4/XGJMP6wW 1SB6IFaQucUCk3oPONYyLp9QyzplF+uvKntn0JXp2I9cVdMxAnEfEjYnQ LjGfOZsvtoTWbOR0y28ww4s1CQjI6PaRIH+fQFbJLv28/ibz1iWE7XxgV 045tkgsrXVkjeggwb1DMP+XYlzB+C59sLTj/7gHt5G2JeWxN6DMCUjJAa CU6/zjuJa5Bg4aNEc+tInIh6QykD06ZbdX/RdgEVioCkywrZrSbQhwQ4h 4c6LJBTsnFMMOhEQdrZl0FFFfHa4kwC4HgSEQrzUZrhx/F+iYLZsIZsgV A==; X-CSE-ConnectionGUID: m55iPwxlTi2zyni+7oxQuQ== X-CSE-MsgGUID: JrOSNuNTT4y1iabFHP7JSg== X-IronPort-AV: E=McAfee;i="6800,10657,11895"; a="88994633" X-IronPort-AV: E=Sophos;i="6.25,260,1779174000"; d="scan'208";a="88994633" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Sep 2026 13:10:37 -0700 X-CSE-ConnectionGUID: SHTISy7IQJmVtoh3HQr45A== X-CSE-MsgGUID: QzV5bgCFQSGpgXVTSBRmsg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,260,1779174000"; d="scan'208";a="273348152" Received: from mjruhl-vm.amr.corp.intel.com ([10.11.186.166]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Sep 2026 13:10:33 -0700 From: "Michael J. Ruhl" To: platform-driver-x86@vger.kernel.org, intel-xe@lists.freedesktop.org, hansg@kernel.org, ilpo.jarvinen@linux.intel.com, matthew.brost@intel.com, rodrigo.vivi@intel.com, thomas.hellstrom@linux.intel.com, airlied@gmail.com, simona@ffwll.ch, david.e.box@linux.intel.com, anoop.c.vijay@intel.com, badal.nilawar@intel.com, matthew.d.roper@intel.com, james.ausmus@intel.com, karthik.poosa@intel.com Subject: [PATCH v5 14/18] drm/xe/vsec: Crescent Island PMT callbacks Date: Thu, 3 Sep 2026 13:10:16 -0700 Message-ID: <20260903201002.1064889-34-michael.j.ruhl@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260903201002.1064889-20-michael.j.ruhl@intel.com> References: <20260903201002.1064889-20-michael.j.ruhl@intel.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit CRI PMT support requires callbacks to access the discovery status and control areas. Access is a common MMIO area that requires an index to be set before access is allowed. Introduce the necessary callbacks to get the status and control information for CRI PMT usage. Add the glue logic to register the CRI PMT functionality. Signed-off-by: Michael J. Ruhl --- drivers/gpu/drm/xe/xe_vsec.c | 108 ++++++++++++++++++++++++++++++++++- 1 file changed, 105 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_vsec.c b/drivers/gpu/drm/xe/xe_vsec.c index 0438810337dd..336c4b7d284b 100644 --- a/drivers/gpu/drm/xe/xe_vsec.c +++ b/drivers/gpu/drm/xe/xe_vsec.c @@ -355,17 +355,110 @@ int xe_pmt_telem_read(struct device *dev, u32 guid, u64 *data, loff_t user_offse return ret == 0 ? count : ret; } -static struct pmt_callbacks xe_pmt_cb = { +/** + * xe_pmt_read_reg() - read a crashlog register + * @dev: the xe device that registered the callback + * @guid: PMT guid of the crashlog instance + * @reg: data read from the PMT data structure + * @offset: which data to read from the PMT data structure + * + * Read the requested PMT register based on the pcie device and guid. The + * supported struct is the Crashlog Type1 Version2. + * + * Currently this is for CRI only. + */ +static int xe_pmt_read_reg(struct device *dev, u32 guid, u32 *reg, u32 offset) +{ + struct xe_device *xe = kdev_to_xe_device(dev); + void __iomem *disc_addr = xe->mmio.regs + xe->pmt.base_offset; + int ret = 0; + u32 inst; + int idx; + + if (!drm_dev_enter(&xe->drm, &idx)) + return -ENODEV; + + if (FIELD_GET(GUID_DEVICE_ID, guid) != CRI_DEVICE_ID || + FIELD_GET(GUID_CAP_TYPE, guid) != CRASHLOG) { + ret = -EINVAL; + goto dev_exit; + } + + inst = FIELD_GET(GUID_RECORD_ID, guid) == PUNIT ? + CRI_CRASHLOG_PUNIT_DISC_OFFSET : CRI_CRASHLOG_OOBMSM_DISC_OFFSET; + disc_addr += inst + offset; + + xe_pm_runtime_get(xe); + mutex_lock(&xe->pmt.lock); + + xe->soc_remapper.set_telem_region(xe, CRI_IDX_TELEM_DISCOVERY); + + memcpy_fromio(reg, disc_addr, sizeof(*reg)); + + mutex_unlock(&xe->pmt.lock); + xe_pm_runtime_put(xe); + +dev_exit: + drm_dev_exit(idx); + + return ret; +} + +static int xe_pmt_write_reg(struct device *dev, u32 guid, u32 reg, u32 offset) +{ + struct xe_device *xe = kdev_to_xe_device(dev); + void __iomem *disc_addr = xe->mmio.regs + xe->pmt.base_offset; + int ret = 0; + u32 inst; + int idx; + + if (!drm_dev_enter(&xe->drm, &idx)) + return -ENODEV; + + if (FIELD_GET(GUID_DEVICE_ID, guid) != CRI_DEVICE_ID || + FIELD_GET(GUID_CAP_TYPE, guid) != CRASHLOG) { + ret = -EINVAL; + goto dev_exit; + } + + inst = FIELD_GET(GUID_RECORD_ID, guid) == PUNIT ? + CRI_CRASHLOG_PUNIT_DISC_OFFSET : CRI_CRASHLOG_OOBMSM_DISC_OFFSET; + disc_addr += inst + offset; + + xe_pm_runtime_get(xe); + mutex_lock(&xe->pmt.lock); + + xe->soc_remapper.set_telem_region(xe, CRI_IDX_TELEM_DISCOVERY); + + memcpy_toio(disc_addr, ®, sizeof(reg)); + + mutex_unlock(&xe->pmt.lock); + xe_pm_runtime_put(xe); + +dev_exit: + drm_dev_exit(idx); + + return ret; +} + +static struct pmt_callbacks xe_bmg_pmt_cb = { .read_telem = xe_pmt_telem_read, }; +static struct pmt_callbacks xe_cri_pmt_cb = { + .read_telem = xe_pmt_telem_read, + .read_reg = xe_pmt_read_reg, + .write_reg = xe_pmt_write_reg, +}; + static const int vsec_platforms[] = { [XE_BATTLEMAGE] = XE_VSEC_BMG, + [XE_CRESCENTISLAND] = XE_VSEC_CRI, }; static enum xe_vsec get_platform_info(struct xe_device *xe) { - if (xe->info.platform > XE_BATTLEMAGE) + if (xe->info.platform > XE_CRESCENTISLAND) return XE_VSEC_UNKNOWN; return vsec_platforms[xe->info.platform]; @@ -395,8 +488,17 @@ void xe_vsec_init(struct xe_device *xe) if (IS_SRIOV_VF(xe)) return; xe->pmt.base_offset = BMG_TELEMETRY_OFFSET; - info->priv_data = &xe_pmt_cb; + info->priv_data = &xe_bmg_pmt_cb; break; + + case XE_VSEC_CRI: + if (IS_SRIOV_VF(xe)) + return; + xe->pmt.base_offset = CRI_PMT_OFFSET; + info->priv_data = &xe_cri_pmt_cb; + xe->soc_remapper.set_telem_region(xe, CRI_IDX_TELEM_DISCOVERY); + break; + default: break; } -- 2.43.0