From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jarkko Sakkinen Subject: Re: [intel-sgx-kernel-dev] [PATCH v11 09/13] x86, sgx: basic routines for enclave page cache Date: Mon, 25 Jun 2018 10:36:47 +0300 Message-ID: <208b7c272ca4a5f01299ec6c89f57b2b00b7866d.camel@linux.intel.com> References: <20180608171216.26521-1-jarkko.sakkinen@linux.intel.com> <20180608171216.26521-10-jarkko.sakkinen@linux.intel.com> <78982a32-c589-48e2-9a83-fd36903b5588@fortanix.com> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org To: Andy Lutomirski , Jethro Beekman Cc: X86 ML , Platform Driver , npmccallum@redhat.com, LKML , Ingo Molnar , intel-sgx-kernel-dev@lists.01.org, "H. Peter Anvin" , Thomas Gleixner List-Id: platform-driver-x86.vger.kernel.org On Mon, 2018-06-18 at 14:33 -0700, Andy Lutomirski wrote: > When KVM host support goes in, even this won't be good enough if we > want to allow passthrough access to the MSRs because we will no longer > be able to guarantee that all zeros is invalid. Instead we'd need an > actual flag saying that the cache is invalid. I'm not sure if I understood this part. If it was pass-through, and there was a flag, how that flag in the host would get updated? /Jarkko