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Reviewed-by: Mario Limonciello > > drivers/platform/x86/amd/pmc/pmc.c | 103 ----------------------------- > drivers/platform/x86/amd/pmc/pmc.h | 103 +++++++++++++++++++++++++++++ > 2 files changed, 103 insertions(+), 103 deletions(-) > > diff --git a/drivers/platform/x86/amd/pmc/pmc.c b/drivers/platform/x86/amd/pmc/pmc.c > index 92adf4523736..943fb85af91d 100644 > --- a/drivers/platform/x86/amd/pmc/pmc.c > +++ b/drivers/platform/x86/amd/pmc/pmc.c > @@ -30,109 +30,6 @@ > > #include "pmc.h" > > -/* SMU communication registers */ > -#define AMD_PMC_REGISTER_MESSAGE 0x538 > -#define AMD_PMC_REGISTER_RESPONSE 0x980 > -#define AMD_PMC_REGISTER_ARGUMENT 0x9BC > - > -/* PMC Scratch Registers */ > -#define AMD_PMC_SCRATCH_REG_CZN 0x94 > -#define AMD_PMC_SCRATCH_REG_YC 0xD14 > - > -/* STB Registers */ > -#define AMD_PMC_STB_PMI_0 0x03E30600 > -#define AMD_PMC_STB_S2IDLE_PREPARE 0xC6000001 > -#define AMD_PMC_STB_S2IDLE_RESTORE 0xC6000002 > -#define AMD_PMC_STB_S2IDLE_CHECK 0xC6000003 > -#define AMD_PMC_STB_DUMMY_PC 0xC6000007 > - > -/* STB S2D(Spill to DRAM) has different message port offset */ > -#define AMD_S2D_REGISTER_MESSAGE 0xA20 > -#define AMD_S2D_REGISTER_RESPONSE 0xA80 > -#define AMD_S2D_REGISTER_ARGUMENT 0xA88 > - > -/* STB Spill to DRAM Parameters */ > -#define S2D_TELEMETRY_BYTES_MAX 0x100000 > -#define S2D_RSVD_RAM_SPACE 0x100000 > -#define S2D_TELEMETRY_DRAMBYTES_MAX 0x1000000 > - > -/* STB Spill to DRAM Message Definition */ > -#define STB_FORCE_FLUSH_DATA 0xCF > - > -/* Base address of SMU for mapping physical address to virtual address */ > -#define AMD_PMC_MAPPING_SIZE 0x01000 > -#define AMD_PMC_BASE_ADDR_OFFSET 0x10000 > -#define AMD_PMC_BASE_ADDR_LO 0x13B102E8 > -#define AMD_PMC_BASE_ADDR_HI 0x13B102EC > -#define AMD_PMC_BASE_ADDR_LO_MASK GENMASK(15, 0) > -#define AMD_PMC_BASE_ADDR_HI_MASK GENMASK(31, 20) > - > -/* SMU Response Codes */ > -#define AMD_PMC_RESULT_OK 0x01 > -#define AMD_PMC_RESULT_CMD_REJECT_BUSY 0xFC > -#define AMD_PMC_RESULT_CMD_REJECT_PREREQ 0xFD > -#define AMD_PMC_RESULT_CMD_UNKNOWN 0xFE > -#define AMD_PMC_RESULT_FAILED 0xFF > - > -/* FCH SSC Registers */ > -#define FCH_S0I3_ENTRY_TIME_L_OFFSET 0x30 > -#define FCH_S0I3_ENTRY_TIME_H_OFFSET 0x34 > -#define FCH_S0I3_EXIT_TIME_L_OFFSET 0x38 > -#define FCH_S0I3_EXIT_TIME_H_OFFSET 0x3C > -#define FCH_SSC_MAPPING_SIZE 0x800 > -#define FCH_BASE_PHY_ADDR_LOW 0xFED81100 > -#define FCH_BASE_PHY_ADDR_HIGH 0x00000000 > - > -/* SMU Message Definations */ > -#define SMU_MSG_GETSMUVERSION 0x02 > -#define SMU_MSG_LOG_GETDRAM_ADDR_HI 0x04 > -#define SMU_MSG_LOG_GETDRAM_ADDR_LO 0x05 > -#define SMU_MSG_LOG_START 0x06 > -#define SMU_MSG_LOG_RESET 0x07 > -#define SMU_MSG_LOG_DUMP_DATA 0x08 > -#define SMU_MSG_GET_SUP_CONSTRAINTS 0x09 > -/* List of supported CPU ids */ > -#define AMD_CPU_ID_RV 0x15D0 > -#define AMD_CPU_ID_RN 0x1630 > -#define AMD_CPU_ID_PCO AMD_CPU_ID_RV > -#define AMD_CPU_ID_CZN AMD_CPU_ID_RN > -#define AMD_CPU_ID_YC 0x14B5 > -#define AMD_CPU_ID_CB 0x14D8 > -#define AMD_CPU_ID_PS 0x14E8 > -#define AMD_CPU_ID_SP 0x14A4 > -#define PCI_DEVICE_ID_AMD_1AH_M20H_ROOT 0x1507 > - > -#define PMC_MSG_DELAY_MIN_US 50 > -#define RESPONSE_REGISTER_LOOP_MAX 20000 > - > -#define DELAY_MIN_US 2000 > -#define DELAY_MAX_US 3000 > -#define FIFO_SIZE 4096 > - > -enum amd_pmc_def { > - MSG_TEST = 0x01, > - MSG_OS_HINT_PCO, > - MSG_OS_HINT_RN, > -}; > - > -enum s2d_arg { > - S2D_TELEMETRY_SIZE = 0x01, > - S2D_PHYS_ADDR_LOW, > - S2D_PHYS_ADDR_HIGH, > - S2D_NUM_SAMPLES, > - S2D_DRAM_SIZE, > -}; > - > -struct amd_pmc_stb_v2_data { > - size_t size; > - u8 data[] __counted_by(size); > -}; > - > -struct amd_pmc_bit_map { > - const char *name; > - u32 bit_mask; > -}; > - > static const struct amd_pmc_bit_map soc15_ip_blk[] = { > {"DISPLAY", BIT(0)}, > {"CPU", BIT(1)}, > diff --git a/drivers/platform/x86/amd/pmc/pmc.h b/drivers/platform/x86/amd/pmc/pmc.h > index 12728eedecda..704256b07ef4 100644 > --- a/drivers/platform/x86/amd/pmc/pmc.h > +++ b/drivers/platform/x86/amd/pmc/pmc.h > @@ -14,6 +14,109 @@ > #include > #include > > +/* SMU communication registers */ > +#define AMD_PMC_REGISTER_MESSAGE 0x538 > +#define AMD_PMC_REGISTER_RESPONSE 0x980 > +#define AMD_PMC_REGISTER_ARGUMENT 0x9BC > + > +/* PMC Scratch Registers */ > +#define AMD_PMC_SCRATCH_REG_CZN 0x94 > +#define AMD_PMC_SCRATCH_REG_YC 0xD14 > + > +/* STB Registers */ > +#define AMD_PMC_STB_PMI_0 0x03E30600 > +#define AMD_PMC_STB_S2IDLE_PREPARE 0xC6000001 > +#define AMD_PMC_STB_S2IDLE_RESTORE 0xC6000002 > +#define AMD_PMC_STB_S2IDLE_CHECK 0xC6000003 > +#define AMD_PMC_STB_DUMMY_PC 0xC6000007 > + > +/* STB S2D(Spill to DRAM) has different message port offset */ > +#define AMD_S2D_REGISTER_MESSAGE 0xA20 > +#define AMD_S2D_REGISTER_RESPONSE 0xA80 > +#define AMD_S2D_REGISTER_ARGUMENT 0xA88 > + > +/* STB Spill to DRAM Parameters */ > +#define S2D_TELEMETRY_BYTES_MAX 0x100000 > +#define S2D_RSVD_RAM_SPACE 0x100000 > +#define S2D_TELEMETRY_DRAMBYTES_MAX 0x1000000 > + > +/* STB Spill to DRAM Message Definition */ > +#define STB_FORCE_FLUSH_DATA 0xCF > + > +/* Base address of SMU for mapping physical address to virtual address */ > +#define AMD_PMC_MAPPING_SIZE 0x01000 > +#define AMD_PMC_BASE_ADDR_OFFSET 0x10000 > +#define AMD_PMC_BASE_ADDR_LO 0x13B102E8 > +#define AMD_PMC_BASE_ADDR_HI 0x13B102EC > +#define AMD_PMC_BASE_ADDR_LO_MASK GENMASK(15, 0) > +#define AMD_PMC_BASE_ADDR_HI_MASK GENMASK(31, 20) > + > +/* SMU Response Codes */ > +#define AMD_PMC_RESULT_OK 0x01 > +#define AMD_PMC_RESULT_CMD_REJECT_BUSY 0xFC > +#define AMD_PMC_RESULT_CMD_REJECT_PREREQ 0xFD > +#define AMD_PMC_RESULT_CMD_UNKNOWN 0xFE > +#define AMD_PMC_RESULT_FAILED 0xFF > + > +/* FCH SSC Registers */ > +#define FCH_S0I3_ENTRY_TIME_L_OFFSET 0x30 > +#define FCH_S0I3_ENTRY_TIME_H_OFFSET 0x34 > +#define FCH_S0I3_EXIT_TIME_L_OFFSET 0x38 > +#define FCH_S0I3_EXIT_TIME_H_OFFSET 0x3C > +#define FCH_SSC_MAPPING_SIZE 0x800 > +#define FCH_BASE_PHY_ADDR_LOW 0xFED81100 > +#define FCH_BASE_PHY_ADDR_HIGH 0x00000000 > + > +/* SMU Message Definations */ > +#define SMU_MSG_GETSMUVERSION 0x02 > +#define SMU_MSG_LOG_GETDRAM_ADDR_HI 0x04 > +#define SMU_MSG_LOG_GETDRAM_ADDR_LO 0x05 > +#define SMU_MSG_LOG_START 0x06 > +#define SMU_MSG_LOG_RESET 0x07 > +#define SMU_MSG_LOG_DUMP_DATA 0x08 > +#define SMU_MSG_GET_SUP_CONSTRAINTS 0x09 > +/* List of supported CPU ids */ > +#define AMD_CPU_ID_RV 0x15D0 > +#define AMD_CPU_ID_RN 0x1630 > +#define AMD_CPU_ID_PCO AMD_CPU_ID_RV > +#define AMD_CPU_ID_CZN AMD_CPU_ID_RN > +#define AMD_CPU_ID_YC 0x14B5 > +#define AMD_CPU_ID_CB 0x14D8 > +#define AMD_CPU_ID_PS 0x14E8 > +#define AMD_CPU_ID_SP 0x14A4 > +#define PCI_DEVICE_ID_AMD_1AH_M20H_ROOT 0x1507 > + > +#define PMC_MSG_DELAY_MIN_US 50 > +#define RESPONSE_REGISTER_LOOP_MAX 20000 > + > +#define DELAY_MIN_US 2000 > +#define DELAY_MAX_US 3000 > +#define FIFO_SIZE 4096 > + > +enum amd_pmc_def { > + MSG_TEST = 0x01, > + MSG_OS_HINT_PCO, > + MSG_OS_HINT_RN, > +}; > + > +enum s2d_arg { > + S2D_TELEMETRY_SIZE = 0x01, > + S2D_PHYS_ADDR_LOW, > + S2D_PHYS_ADDR_HIGH, > + S2D_NUM_SAMPLES, > + S2D_DRAM_SIZE, > +}; > + > +struct amd_pmc_stb_v2_data { > + size_t size; > + u8 data[] __counted_by(size); > +}; > + > +struct amd_pmc_bit_map { > + const char *name; > + u32 bit_mask; > +}; > + > struct amd_pmc_dev { > void __iomem *regbase; > void __iomem *smu_virt_addr;