From: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
To: "Michael J. Ruhl" <michael.j.ruhl@intel.com>
Cc: platform-driver-x86@vger.kernel.org,
intel-xe@lists.freedesktop.org, Hans de Goede <hansg@kernel.org>,
matthew.brost@intel.com, rodrigo.vivi@intel.com,
thomas.hellstrom@linux.intel.com, airlied@gmail.com,
simona@ffwll.ch, david.e.box@linux.intel.com,
anoop.c.vijay@intel.com, badal.nilawar@intel.com,
matthew.d.roper@intel.com, james.ausmus@intel.com,
karthik.poosa@intel.com
Subject: Re: [PATCH v3 06/10] drm/xe/vsec: Support Crescent Island PMT
Date: Tue, 25 Aug 2026 13:19:21 +0300 (EEST) [thread overview]
Message-ID: <4246052e-8308-70bb-baed-22d6ff18ba83@linux.intel.com> (raw)
In-Reply-To: <20260824162317.2450380-18-michael.j.ruhl@intel.com>
On Mon, 24 Aug 2026, Michael J. Ruhl wrote:
> Crescent Island (CRI) supports PMT telemetry and crashlog.
>
> Add Crescent Island (CRI) discovery structure (DVSEC)
> information to allow for Xe registration.
>
> Signed-off-by: Michael J. Ruhl <michael.j.ruhl@intel.com>
> ---
> drivers/gpu/drm/xe/regs/xe_pmt.h | 5 ++++
> drivers/gpu/drm/xe/xe_vsec.c | 46 ++++++++++++++++++++++++++++++--
> 2 files changed, 49 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_pmt.h b/drivers/gpu/drm/xe/regs/xe_pmt.h
> index a62ab05c6b4c..fc9c9cb6a830 100644
> --- a/drivers/gpu/drm/xe/regs/xe_pmt.h
> +++ b/drivers/gpu/drm/xe/regs/xe_pmt.h
> @@ -20,6 +20,11 @@
> #define BMG_TELEMETRY_BASE_OFFSET 0xE0000
> #define BMG_TELEMETRY_OFFSET (SOC_BASE + BMG_TELEMETRY_BASE_OFFSET)
>
> +#define CRI_TELEMETRY_BASE_OFFSET 0xE0000
> +/* for CRI discovery and telemetry are in an indexed window */
> +#define CRI_DISCOVERY_OFFSET (SOC_BASE + CRI_TELEMETRY_BASE_OFFSET)
> +#define CRI_TELEMETRY_OFFSET (SOC_BASE + CRI_TELEMETRY_BASE_OFFSET)
> +
> #define BMG_MODS_RESIDENCY_OFFSET (0x4D0)
> #define BMG_G2_RESIDENCY_OFFSET (0x530)
> #define BMG_G6_RESIDENCY_OFFSET (0x538)
> diff --git a/drivers/gpu/drm/xe/xe_vsec.c b/drivers/gpu/drm/xe/xe_vsec.c
> index 8abe11e6312f..6345b0b4b26b 100644
> --- a/drivers/gpu/drm/xe/xe_vsec.c
> +++ b/drivers/gpu/drm/xe/xe_vsec.c
> @@ -21,8 +21,19 @@
>
> #include "regs/xe_pmt.h"
>
> -/* PMT GUID value for BMG devices. NOTE: this is NOT a PCI id */
> +/* PMT GUID value for BMG and CRI devices. NOTE: this is NOT a PCI id */
> #define BMG_DEVICE_ID 0xE2F8
> +#define CRI_DEVICE_ID 0xE2FA
> +
> +/*
> + * sizeof(Crashlog Type1 Version2) = 0x18 (24) bytes
> + * For BMG and CRI PUNIT and OOBMSMS crashlogs are consecutive.
> + */
> +#define BMG_CRASHLOG_PUNIT_DISC_OFFSET (0x60)
> +#define BMG_CRASHLOG_OOBMSM_DISC_OFFSET (BMG_CRASHLOG_PUNIT_DISC_OFFSET + 0x18)
> +
> +#define CRI_CRASHLOG_PUNIT_DISC_OFFSET (0x80)
> +#define CRI_CRASHLOG_OOBMSM_DISC_OFFSET (CRI_CRASHLOG_PUNIT_DISC_OFFSET + 0x18)
>
> static struct intel_vsec_header bmg_telemetry = {
> .rev = 1,
> @@ -41,7 +52,7 @@ static struct intel_vsec_header bmg_crashlog = {
> .num_entries = 2,
> .entry_size = 6,
> .tbir = 0,
> - .offset = BMG_DISCOVERY_OFFSET + 0x60,
> + .offset = BMG_DISCOVERY_OFFSET + BMG_CRASHLOG_PUNIT_DISC_OFFSET,
> };
>
> static struct intel_vsec_header *bmg_capabilities[] = {
> @@ -50,9 +61,36 @@ static struct intel_vsec_header *bmg_capabilities[] = {
> NULL
> };
>
> +static struct intel_vsec_header cri_telemetry = {
> + .rev = 1,
> + .length = 0x10,
...
> +static struct intel_vsec_header cri_crashlog = {
> + .rev = 1,
> + .length = 0x10,
One could consider using SZ_x for these (if you do, make sure you've the
header for it).
> + .id = VSEC_ID_CRASHLOG,
> + .num_entries = 2,
> + .entry_size = 6,
> + .tbir = 0,
> + .offset = CRI_DISCOVERY_OFFSET + CRI_CRASHLOG_PUNIT_DISC_OFFSET,
> +};
> +
> +static struct intel_vsec_header *cri_capabilities[] = {
> + &cri_telemetry,
> + &cri_crashlog,
> + NULL
> +};
> +
> enum xe_vsec {
> XE_VSEC_UNKNOWN = 0,
> XE_VSEC_BMG,
> + XE_VSEC_CRI,
> };
>
> static struct intel_vsec_platform_info xe_vsec_info[] = {
> @@ -60,6 +98,10 @@ static struct intel_vsec_platform_info xe_vsec_info[] = {
> .caps = VSEC_CAP_TELEMETRY | VSEC_CAP_CRASHLOG,
> .headers = bmg_capabilities,
> },
> + [XE_VSEC_CRI] = {
> + .caps = VSEC_CAP_TELEMETRY | VSEC_CAP_CRASHLOG,
> + .headers = cri_capabilities,
> + },
> { }
> };
>
>
--
i.
next prev parent reply other threads:[~2026-08-25 10:19 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-24 16:23 [PATCH v3 00/10] Crescent Island PMT support Michael J. Ruhl
2026-08-24 16:23 ` [PATCH v3 01/10] platform/x86/intel/pmt: complete pcidev to device update Michael J. Ruhl
2026-08-24 18:56 ` Rodrigo Vivi
2026-08-25 9:40 ` Ilpo Järvinen
2026-08-25 9:25 ` Ilpo Järvinen
2026-08-24 16:23 ` [PATCH v3 02/10] platform/x86/intel/pmt: Add register access callbacks Michael J. Ruhl
2026-08-25 9:34 ` Ilpo Järvinen
2026-08-26 16:13 ` Ruhl, Michael J
2026-08-26 18:30 ` Ilpo Järvinen
2026-08-27 17:05 ` Ruhl, Michael J
2026-08-24 16:23 ` [PATCH v3 03/10] drm/xe/vsec: Protect against missing config Michael J. Ruhl
2026-08-24 16:23 ` [PATCH v3 04/10] drm/xe/vsec: Use correct pm state get Michael J. Ruhl
2026-08-24 19:04 ` Rodrigo Vivi
2026-08-24 16:23 ` [PATCH v3 05/10] drm/xe/vsec: Support possible hotplug exit Michael J. Ruhl
2026-08-24 19:07 ` Rodrigo Vivi
2026-08-24 16:23 ` [PATCH v3 06/10] drm/xe/vsec: Support Crescent Island PMT Michael J. Ruhl
2026-08-24 19:10 ` Rodrigo Vivi
2026-08-25 10:19 ` Ilpo Järvinen [this message]
2026-08-24 16:23 ` [PATCH v3 07/10] drm/xe/vsec: Crescent Island PMT decode Michael J. Ruhl
2026-08-25 10:24 ` Ilpo Järvinen
2026-08-24 16:23 ` [PATCH v3 08/10] drm/xe/vsec: Crescent Island PMT callbacks Michael J. Ruhl
2026-08-24 16:23 ` [PATCH v3 09/10] drm/xe/vsec: Support late bind fw information Michael J. Ruhl
2026-08-24 19:15 ` Rodrigo Vivi
2026-08-26 13:45 ` Ruhl, Michael J
2026-08-25 10:01 ` Ilpo Järvinen
2026-08-24 16:23 ` [PATCH v3 10/10] drm/xe/vsec: Update PMT internal access for CRI Michael J. Ruhl
2026-08-24 19:18 ` Rodrigo Vivi
2026-08-25 10:16 ` Ilpo Järvinen
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