From: "Poosa, Karthik" <karthik.poosa@intel.com>
To: "Michael J. Ruhl" <michael.j.ruhl@intel.com>,
<platform-driver-x86@vger.kernel.org>,
<intel-xe@lists.freedesktop.org>, <hansg@kernel.org>,
<ilpo.jarvinen@linux.intel.com>, <matthew.brost@intel.com>,
<rodrigo.vivi@intel.com>, <thomas.hellstrom@linux.intel.com>,
<airlied@gmail.com>, <simona@ffwll.ch>,
<david.e.box@linux.intel.com>, <anoop.c.vijay@intel.com>,
<badal.nilawar@intel.com>, <matthew.d.roper@intel.com>,
<james.ausmus@intel.com>
Subject: Re: [PATCH v5 16/18] drm/xe/vsec: Add PMT GUID internal access
Date: Fri, 4 Sep 2026 20:44:36 +0530 [thread overview]
Message-ID: <599e779d-6a72-460d-8af6-8a6cdb1e09df@intel.com> (raw)
In-Reply-To: <20260903201002.1064889-36-michael.j.ruhl@intel.com>
On 04-09-2026 01:40, Michael J. Ruhl wrote:
> Xe accesses the PMT infrastructure directly. The current usage is
> supported ONLY by BMG devices.
>
> CRI has further requirements for access.
>
> Add the platform id to the GUID register define and use that for the
> register access.
>
> Add an API to allow access the GUID based on the platform.
>
> Signed-off-by: Michael J. Ruhl <michael.j.ruhl@intel.com>
> ---
> drivers/gpu/drm/xe/regs/xe_pmt.h | 4 ++-
> drivers/gpu/drm/xe/xe_debugfs.c | 3 +-
> drivers/gpu/drm/xe/xe_device_types.h | 2 ++
> drivers/gpu/drm/xe/xe_hwmon.c | 2 +-
> drivers/gpu/drm/xe/xe_pcode.c | 2 +-
> drivers/gpu/drm/xe/xe_vsec.c | 44 ++++++++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_vsec.h | 1 +
> 7 files changed, 54 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_pmt.h b/drivers/gpu/drm/xe/regs/xe_pmt.h
> index 2f6658395587..fb5b5a8648ba 100644
> --- a/drivers/gpu/drm/xe/regs/xe_pmt.h
> +++ b/drivers/gpu/drm/xe/regs/xe_pmt.h
> @@ -10,7 +10,7 @@
> #define BMG_PMT_BASE_OFFSET 0xDB000
> #define BMG_DISCOVERY_OFFSET (SOC_BASE + BMG_PMT_BASE_OFFSET)
>
> -#define PUNIT_TELEMETRY_GUID XE_REG(BMG_DISCOVERY_OFFSET + 0x4)
> +#define BMG_PUNIT_TELEMETRY_GUID XE_REG(BMG_DISCOVERY_OFFSET + 0x4)
> #define BMG_ENERGY_STATUS_PMT_OFFSET (0x30)
> #define ENERGY_PKG REG_GENMASK64(31, 0)
> #define ENERGY_CARD REG_GENMASK64(63, 32)
> @@ -24,6 +24,8 @@
> /* for CRI discovery and telemetry are in an indexed window */
> #define CRI_PMT_OFFSET (SOC_BASE + XE_PMT_BASE_OFFSET)
>
> +#define CRI_PUNIT_TELEMETRY_GUID XE_REG(CRI_PMT_OFFSET + 0x4)
> +
> #define BMG_MODS_RESIDENCY_OFFSET (0x4D0)
> #define BMG_G2_RESIDENCY_OFFSET (0x530)
> #define BMG_G6_RESIDENCY_OFFSET (0x538)
> diff --git a/drivers/gpu/drm/xe/xe_debugfs.c b/drivers/gpu/drm/xe/xe_debugfs.c
> index 28135f84e286..b01f1e649b51 100644
> --- a/drivers/gpu/drm/xe/xe_debugfs.c
> +++ b/drivers/gpu/drm/xe/xe_debugfs.c
> @@ -101,10 +101,11 @@ static void read_residency_counter(struct xe_device *xe, struct xe_mmio *mmio,
> u32 offset, const char *name, struct drm_printer *p)
> {
> u64 residency = 0;
> +
this can be removed
> int ret;
>
> ret = xe_pmt_telem_read(xe->drm.dev,
> - xe_mmio_read32(mmio, PUNIT_TELEMETRY_GUID),
> + xe_mmio_read32(mmio, BMG_PUNIT_TELEMETRY_GUID),
> &residency, offset, sizeof(residency));
> if (ret != sizeof(residency)) {
> drm_warn(&xe->drm, "%s counter failed to read, ret %d\n", name, ret);
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index 69e052ac5a82..2a8c519e1639 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -473,6 +473,8 @@ struct xe_device {
> struct delayed_work work;
> /** @pmt.retry_count: late-bind probe retry */
> u32 retry_count;
> + /** @pmt.punit_guid_cache: cache of the PUINT GUID */
> + u32 punit_guid_cache;
> } pmt;
>
> /** @soc_remapper: SoC remapper object */
> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index 5284cab6703d..b9740224e07f 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> @@ -519,7 +519,7 @@ xe_hwmon_energy_get(struct xe_hwmon *hwmon, int channel, long *energy)
> u64 pmt_val;
>
> ret = xe_pmt_telem_read(hwmon->xe->drm.dev,
> - xe_mmio_read32(mmio, PUNIT_TELEMETRY_GUID),
> + xe_mmio_read32(mmio, BMG_PUNIT_TELEMETRY_GUID),
> &pmt_val, BMG_ENERGY_STATUS_PMT_OFFSET, sizeof(pmt_val));
> if (ret != sizeof(pmt_val)) {
> drm_warn(&hwmon->xe->drm, "energy read from pmt failed, ret %d\n", ret);
> diff --git a/drivers/gpu/drm/xe/xe_pcode.c b/drivers/gpu/drm/xe/xe_pcode.c
> index d502205bb72a..844d8c6face6 100644
> --- a/drivers/gpu/drm/xe/xe_pcode.c
> +++ b/drivers/gpu/drm/xe/xe_pcode.c
> @@ -369,7 +369,7 @@ int xe_get_pcode_version(struct xe_device *xe, struct xe_pcode_version *version)
> guard(xe_pm_runtime)(xe);
>
> ret = xe_pmt_telem_read(xe->drm.dev,
> - xe_mmio_read32(xe_root_tile_mmio(xe), PUNIT_TELEMETRY_GUID),
> + xe_mmio_read32(xe_root_tile_mmio(xe), BMG_PUNIT_TELEMETRY_GUID),
> (u64 *)version, PUNIT_VERSION_OFFSET, sizeof(*version));
> if (ret != sizeof(*version)) {
> xe_warn(xe, "pcode version read from PMT failed, ret %pe\n", ERR_PTR(ret));
> diff --git a/drivers/gpu/drm/xe/xe_vsec.c b/drivers/gpu/drm/xe/xe_vsec.c
> index 48cacd23b071..896dfb011baf 100644
> --- a/drivers/gpu/drm/xe/xe_vsec.c
> +++ b/drivers/gpu/drm/xe/xe_vsec.c
> @@ -566,6 +566,50 @@ static void vsec_disable_late_bind_work(void *arg)
> xe_pm_runtime_put(xe);
> }
>
> +int xe_vsec_get_guid(struct xe_device *xe, u32 *guid)
> +{
> + struct xe_mmio *mmio = xe_root_tile_mmio(xe);
> + int ret = 0;
> +
> + if (IS_SRIOV_VF(xe))
> + return -EINVAL;
> +
> + if (!xe_pm_runtime_get_if_active(xe))
> + return -ENODATA;
> +
> + mutex_lock(&xe->pmt.lock);
> +
> + if (xe->pmt.punit_guid_cache) {
> + *guid = xe->pmt.punit_guid_cache;
> + goto unlock;
> + }
can you add a comment here that guid doesn't change after first read.
> +
> + switch (xe->info.platform) {
> + case XE_BATTLEMAGE:
> + *guid = xe_mmio_read32(mmio, BMG_PUNIT_TELEMETRY_GUID);
> + break;
> +
> + case XE_CRESCENTISLAND:
> + xe->soc_remapper.set_telem_region(xe, CRI_IDX_TELEM_DISCOVERY);
> + *guid = xe_mmio_read32(mmio, CRI_PUNIT_TELEMETRY_GUID);
> + break;
> +
> + default:
> + *guid = 0;
> + drm_err(&xe->drm, "Unsupported platform: %u\n", xe->info.platform);
> + ret = -EINVAL;
> + break;
> + }
> +
> + xe->pmt.punit_guid_cache = *guid;
you can set cache only when guid is valid
if(*guid)
xe->pmt.punit_guid_cache = *guid;
> +
> +unlock:
> + mutex_unlock(&xe->pmt.lock);
> + xe_pm_runtime_put(xe);
> +
> + return ret;
> +}
> +
> /**
> * xe_vsec_init - Initialize resources and add intel_vsec auxiliary
> * interface
> diff --git a/drivers/gpu/drm/xe/xe_vsec.h b/drivers/gpu/drm/xe/xe_vsec.h
> index c4a1e2fc67d8..50187fdc1207 100644
> --- a/drivers/gpu/drm/xe/xe_vsec.h
> +++ b/drivers/gpu/drm/xe/xe_vsec.h
> @@ -10,6 +10,7 @@ struct device;
> struct xe_device;
>
> int xe_vsec_init(struct xe_device *xe);
> +int xe_vsec_get_guid(struct xe_device *xe, u32 *guid);
> int xe_pmt_telem_read(struct device *dev, u32 guid, u64 *data, loff_t user_offset, u32 count);
>
> #endif
next prev parent reply other threads:[~2026-09-04 15:14 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-03 20:10 [PATCH v5 00/18] Crescent Island PMT support Michael J. Ruhl
2026-09-03 20:10 ` [PATCH v5 01/18] platform/x86/intel/pmt: complete pcidev to device update Michael J. Ruhl
2026-09-03 20:10 ` [PATCH v5 02/18] platform/x86/intel/pmt: refactor rmw with a return value Michael J. Ruhl
2026-09-03 20:10 ` [PATCH v5 03/18] platform/x86/intel/pmt: refactor rc " Michael J. Ruhl
2026-09-03 20:10 ` [PATCH v5 04/18] platform/x86/intel/pmt: Add register access callbacks Michael J. Ruhl
2026-09-03 20:10 ` [PATCH v5 05/18] platform/x86/intel/pmt: Do not remap when using callbacks Michael J. Ruhl
2026-09-03 20:10 ` [PATCH v5 06/18] drm/xe/vsec: Do not register BMG PMT for VF Michael J. Ruhl
2026-09-03 20:10 ` [PATCH v5 07/18] drm/xe/vsec: Correct locking order Michael J. Ruhl
2026-09-03 20:10 ` [PATCH v5 08/18] drm/xe/vsec: Use correct pm state get Michael J. Ruhl
2026-09-03 20:10 ` [PATCH v5 09/18] drm/xe/vsec: Add DOC text for VSEC Michael J. Ruhl
2026-09-03 20:10 ` [PATCH v5 10/18] drm/xe/vsec: Support possible hotplug exit Michael J. Ruhl
2026-09-03 20:10 ` [PATCH v5 11/18] drm/xe/vsec: Support Crescent Island PMT Michael J. Ruhl
2026-09-03 20:10 ` [PATCH v5 12/18] drm/xe/vsec: Refactor BattleMage PMT defines Michael J. Ruhl
2026-09-03 20:10 ` [PATCH v5 13/18] drm/xe/vsec: Crescent Island PMT decode Michael J. Ruhl
2026-09-03 20:10 ` [PATCH v5 14/18] drm/xe/vsec: Crescent Island PMT callbacks Michael J. Ruhl
2026-09-03 20:10 ` [PATCH v5 15/18] drm/xe/vsec: Support late bind fw information Michael J. Ruhl
2026-09-03 20:10 ` [PATCH v5 16/18] drm/xe/vsec: Add PMT GUID internal access Michael J. Ruhl
2026-09-04 15:14 ` Poosa, Karthik [this message]
2026-09-04 16:00 ` Ruhl, Michael J
2026-09-03 20:10 ` [PATCH v5 17/18] drm/xe/vsec: Update PMT " Michael J. Ruhl
2026-09-03 20:10 ` [PATCH v5 18/18] drm/xe/vsec: Refactor platform check Michael J. Ruhl
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