From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Bhardwaj, Rajneesh" Subject: Re: [PATCH v3 3/3] platform/x86: intel_pmc_core: Decode Snoop / Non Snoop LTR Date: Tue, 6 Nov 2018 02:30:41 +0530 Message-ID: <8021ed8d-6931-3ffd-6e46-630e9a2c4a66@linux.intel.com> References: <20181102103441.21943-1-rajneesh.bhardwaj@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org To: Andy Shevchenko Cc: Platform Driver , Darren Hart , Andy Shevchenko , Linux Kernel Mailing List , Rajneesh Bhardwaj , Srinivas Pandruvada List-Id: platform-driver-x86.vger.kernel.org On 03-Nov-18 12:02 AM, Andy Shevchenko wrote: > On Fri, Nov 2, 2018 at 12:37 PM Rajneesh Bhardwaj > wrote: >> The LTR values follow PCIE LTR encoding format and can be decoded as per >> https://pcisig.com/sites/default/files/specification_documents/ECN_LatencyTolnReporting_14Aug08.pdf >> >> This adds support to translate the raw LTR values as read from the PMC >> to meaningful values in nanosecond units of time. >> +#include > I told you something different, i.e. put this header where you _use_ > it, i.o.w into the header file. Oops! Will move it to the header. > >> +#define LTR_REQ_NONSNOOP BIT(31) >> +#define LTR_REQ_SNOOP BIT(15) >> +#define LTR_DECODED_VAL GENMASK(9, 0) >> +#define LTR_DECODED_SCALE GENMASK(12, 10) > If these are in one register, please keep ordered by start bit. Sure, will do. > > The rest is fine. > Many thanks again for your detailed review.