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[35.185.214.157]) by smtp.gmail.com with ESMTPSA id r7sm20049373pgm.15.2021.12.30.10.52.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Dec 2021 10:52:55 -0800 (PST) Date: Thu, 30 Dec 2021 18:52:52 +0000 From: Sean Christopherson To: Brijesh Singh Cc: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-efi@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-coco@lists.linux.dev, linux-mm@kvack.org, Thomas Gleixner , Ingo Molnar , Joerg Roedel , Tom Lendacky , "H. Peter Anvin" , Ard Biesheuvel , Paolo Bonzini , Vitaly Kuznetsov , Jim Mattson , Andy Lutomirski , Dave Hansen , Sergio Lopez , Peter Gonda , Peter Zijlstra , Srinivas Pandruvada , David Rientjes , Dov Murik , Tobin Feldman-Fitzthum , Borislav Petkov , Michael Roth , Vlastimil Babka , "Kirill A . Shutemov" , Andi Kleen , "Dr . David Alan Gilbert" , tony.luck@intel.com, marcorr@google.com, sathyanarayanan.kuppuswamy@linux.intel.com Subject: Re: [PATCH v8 22/40] x86/sev: move MSR-based VMGEXITs for CPUID to helper Message-ID: References: <20211210154332.11526-1-brijesh.singh@amd.com> <20211210154332.11526-23-brijesh.singh@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20211210154332.11526-23-brijesh.singh@amd.com> Precedence: bulk List-ID: X-Mailing-List: platform-driver-x86@vger.kernel.org On Fri, Dec 10, 2021, Brijesh Singh wrote: > From: Michael Roth > > This code will also be used later for SEV-SNP-validated CPUID code in > some cases, so move it to a common helper. > > Signed-off-by: Michael Roth > Signed-off-by: Brijesh Singh > --- > arch/x86/kernel/sev-shared.c | 84 +++++++++++++++++++++++++----------- > 1 file changed, 58 insertions(+), 26 deletions(-) > > diff --git a/arch/x86/kernel/sev-shared.c b/arch/x86/kernel/sev-shared.c > index 3aaef1a18ffe..d89481b31022 100644 > --- a/arch/x86/kernel/sev-shared.c > +++ b/arch/x86/kernel/sev-shared.c > @@ -194,6 +194,58 @@ enum es_result sev_es_ghcb_hv_call(struct ghcb *ghcb, bool set_ghcb_msr, > return verify_exception_info(ghcb, ctxt); > } > > +static int sev_cpuid_hv(u32 func, u32 subfunc, u32 *eax, u32 *ebx, Having @subfunc, a.k.a. index, in is weird/confusing/fragile because it's not consumed, nor is it checked. Peeking ahead, it looks like all future users pass '0'. Taking the index but dropping it on the floor is asking for future breakage. Either drop it or assert that it's zero. > + u32 *ecx, u32 *edx) > +{ > + u64 val; > + > + if (eax) { > + sev_es_wr_ghcb_msr(GHCB_CPUID_REQ(func, GHCB_CPUID_REQ_EAX)); > + VMGEXIT(); > + val = sev_es_rd_ghcb_msr(); > + > + if (GHCB_RESP_CODE(val) != GHCB_MSR_CPUID_RESP) > + return -EIO; > + > + *eax = (val >> 32); > + } > + > + if (ebx) { > + sev_es_wr_ghcb_msr(GHCB_CPUID_REQ(func, GHCB_CPUID_REQ_EBX)); > + VMGEXIT(); > + val = sev_es_rd_ghcb_msr(); > + > + if (GHCB_RESP_CODE(val) != GHCB_MSR_CPUID_RESP) > + return -EIO; > + > + *ebx = (val >> 32); > + } > + > + if (ecx) { > + sev_es_wr_ghcb_msr(GHCB_CPUID_REQ(func, GHCB_CPUID_REQ_ECX)); > + VMGEXIT(); > + val = sev_es_rd_ghcb_msr(); > + > + if (GHCB_RESP_CODE(val) != GHCB_MSR_CPUID_RESP) > + return -EIO; > + > + *ecx = (val >> 32); > + } > + > + if (edx) { > + sev_es_wr_ghcb_msr(GHCB_CPUID_REQ(func, GHCB_CPUID_REQ_EDX)); > + VMGEXIT(); > + val = sev_es_rd_ghcb_msr(); > + > + if (GHCB_RESP_CODE(val) != GHCB_MSR_CPUID_RESP) > + return -EIO; > + > + *edx = (val >> 32); > + } That's a lot of pasta! If you add static int __sev_cpuid_hv(u32 func, int reg_idx, u32 *reg) { u64 val; if (!reg) return 0; sev_es_wr_ghcb_msr(GHCB_CPUID_REQ(func, reg_idx)); VMGEXIT(); val = sev_es_rd_ghcb_msr(); if (GHCB_RESP_CODE(val) != GHCB_MSR_CPUID_RESP) return -EIO; *reg = (val >> 32); return 0; } then this helper can become something like: static int sev_cpuid_hv(u32 func, u32 *eax, u32 *ebx, u32 *ecx, u32 *edx) { int ret; ret = __sev_cpuid_hv(func, GHCB_CPUID_REQ_EAX, eax); ret = ret ? : __sev_cpuid_hv(func, GHCB_CPUID_REQ_EBX, ebx); ret = ret ? : __sev_cpuid_hv(func, GHCB_CPUID_REQ_ECX, ecx); ret = ret ? : __sev_cpuid_hv(func, GHCB_CPUID_REQ_EDX, edx); return ret; } > + > + return 0; > +} > +