Re: [PATCH v9 01/13] Documentation: x86: Add AMD Hardware Feedback Interface documentation

[Mario Limonciello <superm1@kernel.org>]

On 4/28/2025 1:39 PM, Konrad Rzeszutek Wilk wrote:
> ..snip..
>> +Implementation details for Linux
>> +--------------------------------
>> +
>> +The implementation of threads scheduling consists of the following steps:
>> +
>> +1. A thread is spawned and scheduled to the ideal core using the default
>> +   heterogeneous scheduling policy.
>> +2. The processor profiles thread execution and assigns an enumerated
>> +   classification ID.
>> +   This classification is communicated to the OS via logical processor
>> +   scope MSR.
>> +3. During the thread context switch out the operating system consumes the
>> +   workload(WL) classification which resides in a logical processor scope MSR.
>> +4. The OS triggers the hardware to clear its history by writing to an MSR,
>> +   after consuming the WL classification and before switching in the new thread.
>> +5. If due to the classification, ranking table, and processor availability,
>> +   the thread is not on its ideal processor, the OS will then consider
>> +   scheduling the thread on its ideal processor (if available).
> 
> Can you expand on 5) please?  The one patch in this patchset that
> touches the process file just does an WRMSR.

Hi, thanks for looking.

This scheduler change is not first part of the series and is going to be 
a follow up series.

I left it in the documentation as it explains the intended implementation.