Re: [PATCH v2] platform/x86: amd-pmc: Use correct IP block table for AMD 1Ah M80H SoC

[Mario Limonciello <superm1@kernel.org>]

On 7/7/26 07:28, Shyam Sundar S K wrote:
> PMFW reports the S0i3 subsystem accounting per SoC, and the set of IP
> blocks and their bit ordering differ across SoC generations. Family
> 1Ah, Model 80h accounts for a distinct set of 19 IP blocks, which does
> not match the ordering in soc15_ip_blk[].
> 
> Commit 043af31c8d30 ("platform/x86/amd/pmc: Add PMC driver support for
> AMD 1Ah M80H SoC") wired amd_1ah_m80_cpu_info to soc15_ip_blk[], so
> M80H has been reporting incorrect S0i3 accounting via debugfs.
> 
> Add soc15_ip_blk_v3[] with the correct ordering and point
> amd_1ah_m80_cpu_info at it.
> 
> Fixes: 043af31c8d30 ("platform/x86/amd/pmc: Add PMC driver support for AMD 1Ah M80H SoC")
> Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org>
> ---
> v2:
> - Clarified the commit message: the IP block layout is tied to the
>    SoC, not to a firmware version (v1 wording "latest firmware" was
>    misleading). [Ilpo]
> - Reframed as a fix for the wrong table wired up in 043af31c8d30 and
>    added the Fixes: tag. [Ilpo]
> - No functional change from v1 in the code; only the changelog and
>    Fixes: tag are updated.
> 
>   drivers/platform/x86/amd/pmc/pmc.c | 26 ++++++++++++++++++++++++--
>   1 file changed, 24 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/platform/x86/amd/pmc/pmc.c b/drivers/platform/x86/amd/pmc/pmc.c
> index d50ea62fa2f3..4a5650f1a3a8 100644
> --- a/drivers/platform/x86/amd/pmc/pmc.c
> +++ b/drivers/platform/x86/amd/pmc/pmc.c
> @@ -33,6 +33,28 @@
>   
>   #include "pmc.h"
>   
> +static const struct amd_pmc_bit_map soc15_ip_blk_v3[] = {
> +	{"VDDCR",	BIT(0)},
> +	{"VDDCR_LP",	BIT(1)},
> +	{"LSOCV",	BIT(2)},
> +	{"DISPLAY",	BIT(3)},
> +	{"VCN",		BIT(4)},
> +	{"JPEG",	BIT(5)},
> +	{"UMSCH",	BIT(6)},
> +	{"VPE",		BIT(7)},
> +	{"MPM",		BIT(8)},
> +	{"NPU",		BIT(9)},
> +	{"USB_HC0",	BIT(10)},
> +	{"eUSB_HC0",	BIT(11)},
> +	{"RT0_ADP_HC1", BIT(12)},
> +	{"RT1_ADP_HC1", BIT(13)},
> +	{"RT2_ADP_HC2", BIT(14)},
> +	{"USB4_RT0",	BIT(15)},
> +	{"USB4_RT1",	BIT(16)},
> +	{"USB4-RT2",	BIT(17)},
> +	{"LAPIC",	BIT(18)},
> +};
> +
>   static const struct amd_pmc_bit_map soc15_ip_blk_v2[] = {
>   	{"DISPLAY",     BIT(0)},
>   	{"CPU",         BIT(1)},
> @@ -159,9 +181,9 @@ static const struct amd_pmc_cpu_info amd_1ah_m80_cpu_info = {
>   	.smu_msg	= AMD_PMC_REGISTER_MSG_1AH_80H,
>   	.smu_arg	= AMD_PMC_REGISTER_ARG_1AH_80H,
>   	.smu_rsp	= AMD_PMC_REGISTER_RSP_1AH_80H,
> -	.num_ips	= ARRAY_SIZE(soc15_ip_blk),
> +	.num_ips	= ARRAY_SIZE(soc15_ip_blk_v3),
>   	.scratch_reg	= AMD_PMC_SCRATCH_REG_1AH,
> -	.ips_ptr	= soc15_ip_blk,
> +	.ips_ptr	= soc15_ip_blk_v3,
>   	.os_hint	= MSG_OS_HINT_RN,
>   };
>