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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id e21sm720981ita.28.2018.02.08.14.10.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Feb 2018 14:10:32 -0800 (PST) Subject: Re: [Qemu-devel] [PATCH v2 16/32] arm/translate-a64: add FP16 x2 ops for simd_indexed To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-arm@nongnu.org Cc: Peter Maydell , qemu-devel@nongnu.org References: <20180208173157.24705-1-alex.bennee@linaro.org> <20180208173157.24705-17-alex.bennee@linaro.org> From: Richard Henderson Message-ID: <01476a36-ea99-e11b-ce2c-8752cc6e8b2c@linaro.org> Date: Thu, 8 Feb 2018 14:10:31 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 MIME-Version: 1.0 In-Reply-To: <20180208173157.24705-17-alex.bennee@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-TUID: M5pMzHCti2I3 On 02/08/2018 09:31 AM, Alex Bennée wrote: > A bunch of the vectorised bitwise operations just operate on larger > chunks at a time. We can do the same for the new half-precision > operations by introducing some TWOHALFOP helpers which work on each > half of a pair of half-precision operations at once. > > Hopefully all this hoop jumping will get simpler once we have > generically vectorised helpers here. > > Signed-off-by: Alex Bennée > > --- > v2 > - checkpatch fixes > --- > target/arm/helper-a64.c | 46 +++++++++++++++++++++++++++++++++++++++++++++- > target/arm/helper-a64.h | 10 ++++++++++ > target/arm/translate-a64.c | 36 +++++++++++++++++++++++++++++------- > 3 files changed, 84 insertions(+), 8 deletions(-) Reviewed-by: Richard Henderson r~