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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-475dcbe5587sm164670195e9.0.2025.10.27.06.33.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 27 Oct 2025 06:33:27 -0700 (PDT) Message-ID: <0199c5ce-9bb2-42f5-b545-8aaaf47364b0@linaro.org> Date: Mon, 27 Oct 2025 14:33:25 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/6] hw: Log unassigned MMIO accesses with unassigned_mem_ops Content-Language: en-US To: Peter Maydell , =?UTF-8?Q?Alex_Benn=C3=A9e?= Cc: qemu-devel@nongnu.org, Joel Stanley , qemu-arm@nongnu.org, =?UTF-8?Q?C=C3=A9dric_Le_Goater?= , David Hildenbrand , Gerd Hoffmann , Troy Lee , Paolo Bonzini , Helge Deller , Mark Cave-Ayland , Richard Henderson , Steven Lee , Andrew Jeffery , Peter Xu , Artyom Tarasenko , Jamin Lin References: <20251027123644.63487-1-philmd@linaro.org> <87pla8xzd2.fsf@draig.linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org On 27/10/25 14:26, Peter Maydell wrote: > On Mon, 27 Oct 2025 at 13:12, Alex Bennée wrote: >> >> Philippe Mathieu-Daudé writes: >> >>> Do not log unassigned MMIO accesses as I/O ones: >>> expose unassigned_mem_ops then use it instead of >>> unassigned_io_ops. >> >> But why? Is it because ioport.c is a x86 io thing? > > > There is a behaviour difference: unassigned_mem_ops > will fault (because of unassigned_mem_accepts()), > but unassigned_io_ops will be "reads as -1, writes > are ignored". This patch series doesn't mention any > intention of introducing a behaviour difference, so > I suspect this is not intended... Oops... Good catch. > There are a couple of different but related concepts > here that we need to keep straight: > > (1) x86 I/O ops, which are different CPU instructions > that talk to a different memory-space than MMIO > accesses. In QEMU we model these as accesses to the > address_space_io AddressSpace. I believe no other > target CPU has an equivalent to this. This is also my understanding. > (2) PCI "I/O" BARs. PCI devices can have both MMIO > and IO BARs. A PCI controller on x86 maps IO BARs > into the IO space, I think. On non-x86 the IO BARs > typically appear in a different window for MMIO > accesses. Behaviour of PCI I/O accesses to unimplemented > regions is probably defined by the PCI spec somewhere. > Behaviour of PCI accesses to unimplemented MMIO > window areas is I think technically left unspecified > by the PCI standard, but "write ignore/read -1" is > what x86 does and what most software expects, so > hardware that implements something else is making > its life unnecessarily difficult. Right, this is what I'd like to unify, ... > I suspect we entangle the PCI IO BAR concept and > implementation a bit more with the x86 I/O ops > implementation than we ideally ought to. ... to disentangle that.