From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Cc: patches@linaro.org, qemu-arm@nongnu.org,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Andreas Färber" <afaerber@suse.de>
Subject: [PATCH v3 14/19] target-arm: Implement asidx_from_attrs
Date: Thu, 14 Jan 2016 13:52:50 +0000 [thread overview]
Message-ID: <1452779575-32582-15-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1452779575-32582-1-git-send-email-peter.maydell@linaro.org>
Implement the asidx_from_attrs CPU method to return the
Secure or NonSecure address space as appropriate.
(The function is inline so we can use it directly in target-arm
code to be added in later patches.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
target-arm/cpu.c | 1 +
target-arm/cpu.h | 8 ++++++++
2 files changed, 9 insertions(+)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 34caa1b..ab0021e 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -1451,6 +1451,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->do_interrupt = arm_cpu_do_interrupt;
cc->do_unaligned_access = arm_cpu_do_unaligned_access;
cc->get_phys_page_debug = arm_cpu_get_phys_page_debug;
+ cc->asidx_from_attrs = arm_asidx_from_attrs;
cc->vmsd = &vmstate_arm_cpu;
cc->virtio_is_big_endian = arm_cpu_is_big_endian;
#endif
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 9108b5b..ee873b7 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -1997,4 +1997,12 @@ enum {
QEMU_PSCI_CONDUIT_HVC = 2,
};
+#ifndef CONFIG_USER_ONLY
+/* Return the address space index to use for a memory access */
+static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
+{
+ return attrs.secure ? ARMASIdx_S : ARMASIdx_NS;
+}
+#endif
+
#endif
--
1.9.1
next prev parent reply other threads:[~2016-01-14 14:18 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-01-14 13:52 [PATCH v3 00/19] Add support for multiple address spaces per CPU and use it for ARM TrustZone Peter Maydell
2016-01-14 13:52 ` [PATCH v3 01/19] exec.c: Don't set cpu->as until cpu_address_space_init Peter Maydell
2016-01-14 13:52 ` [PATCH v3 02/19] exec.c: Allow target CPUs to define multiple AddressSpaces Peter Maydell
2016-01-14 13:52 ` [PATCH v3 03/19] exec-all.h: Document tlb_set_page_with_attrs, tlb_set_page Peter Maydell
2016-01-14 13:52 ` [PATCH v3 04/19] cpu: Add new get_phys_page_attrs_debug() method Peter Maydell
2016-01-14 13:52 ` [PATCH v3 05/19] cpu: Add new asidx_from_attrs() method Peter Maydell
2016-01-14 13:52 ` [PATCH v3 06/19] cputlb.c: Use correct address space when looking up MemoryRegionSection Peter Maydell
2016-01-14 13:52 ` [PATCH v3 07/19] exec.c: Pass MemTxAttrs to iotlb_to_region so it uses the right AS Peter Maydell
2016-01-14 13:52 ` [PATCH v3 08/19] exec.c: Add cpu_get_address_space() Peter Maydell
2016-01-14 13:52 ` [PATCH v3 09/19] exec.c: Use cpu_get_phys_page_attrs_debug Peter Maydell
2016-01-14 13:52 ` [PATCH v3 10/19] exec.c: Use correct AddressSpace in watch_mem_read and watch_mem_write Peter Maydell
2016-01-14 13:52 ` [PATCH v3 11/19] memory: Add address_space_init_shareable() Peter Maydell
2016-01-14 13:52 ` [PATCH v3 12/19] qom/cpu: Add MemoryRegion property Peter Maydell
2016-01-14 23:37 ` [Qemu-arm] " Peter Crosthwaite
2016-01-14 13:52 ` [PATCH v3 13/19] target-arm: Add QOM property for Secure memory region Peter Maydell
2016-01-14 13:52 ` Peter Maydell [this message]
2016-01-14 13:52 ` [PATCH v3 15/19] target-arm: Implement cpu_get_phys_page_attrs_debug Peter Maydell
2016-01-14 13:52 ` [PATCH v3 16/19] target-arm: Support multiple address spaces in page table walks Peter Maydell
2016-01-14 13:52 ` [PATCH v3 17/19] hw/arm/virt: Wire up memory region to CPUs explicitly Peter Maydell
2016-01-14 13:52 ` [PATCH v3 18/19] hw/arm/virt: add secure memory region and UART Peter Maydell
2016-01-14 13:52 ` [PATCH v3 19/19] HACK: rearrange the virt memory map to suit OP-TEE Peter Maydell
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