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[80.15.154.113]) by smtp.googlemail.com with ESMTPSA id id1sm9999337wjb.19.2016.01.15.02.37.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 15 Jan 2016 02:37:54 -0800 (PST) From: Alvise Rigo To: qemu-devel@nongnu.org Date: Fri, 15 Jan 2016 11:37:42 +0100 Message-Id: <1452854262-19550-1-git-send-email-a.rigo@virtualopensystems.com> X-Mailer: git-send-email 2.7.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::241 Cc: Peter Maydell , tech@virtualopensystems.com, Alvise Rigo , "open list:ARM" Subject: [Qemu-arm] [Qemu-devel] [PATCH v2] target-arm: Use the right MMU index in arm_regime_using_lpae_format X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org X-TUID: t/SxslO2wOTH arm_regime_using_lpae_format checks whether the LPAE extension is used for stage 1 translation regimes. MMU indexes not exclusively of a stage 1 regime won't work with this method. In case of ARMMMUIdx_S12NSE0 or ARMMMUIdx_S12NSE1, offset these values by ARMMMUIdx_S1NSE0 to get the right index indicating a stage 1 translation regime. Rename also the function to arm_s1_regime_using_lpae_format and update the comments to reflect the change. Signed-off-by: Alvise Rigo --- target-arm/helper.c | 12 ++++++++---- target-arm/internals.h | 5 +++-- target-arm/op_helper.c | 2 +- 3 files changed, 12 insertions(+), 7 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 59d5a41..faeaaa8 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -5996,11 +5996,15 @@ static inline bool regime_using_lpae_format(CPUARMState *env, return false; } -/* Returns true if the translation regime is using LPAE format page tables. - * Used when raising alignment exceptions, whose FSR changes depending on - * whether the long or short descriptor format is in use. */ -bool arm_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) +/* Returns true if the stage 1 translation regime is using LPAE format page + * tables. Used when raising alignment exceptions, whose FSR changes depending + * on whether the long or short descriptor format is in use. */ +bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) { + if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { + mmu_idx += ARMMMUIdx_S1NSE0; + } + return regime_using_lpae_format(env, mmu_idx); } diff --git a/target-arm/internals.h b/target-arm/internals.h index b925aaa..d226bbe 100644 --- a/target-arm/internals.h +++ b/target-arm/internals.h @@ -441,8 +441,9 @@ struct ARMMMUFaultInfo { bool arm_tlb_fill(CPUState *cpu, vaddr address, int rw, int mmu_idx, uint32_t *fsr, ARMMMUFaultInfo *fi); -/* Return true if the translation regime is using LPAE format page tables */ -bool arm_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx); +/* Return true if the stage 1 translation regime is using LPAE format page + * tables */ +bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx); /* Raise a data fault alignment exception for the specified virtual address */ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, int is_write, diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index e42d287..951fc5a 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -149,7 +149,7 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, int is_write, /* the DFSR for an alignment fault depends on whether we're using * the LPAE long descriptor format, or the short descriptor format */ - if (arm_regime_using_lpae_format(env, cpu_mmu_index(env, false))) { + if (arm_s1_regime_using_lpae_format(env, cpu_mmu_index(env, false))) { env->exception.fsr = 0x21; } else { env->exception.fsr = 0x1; -- 2.7.0