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[52.8.89.49]) by smtp.gmail.com with ESMTPSA id m16sm19976134pfi.75.2016.02.12.06.37.11 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Fri, 12 Feb 2016 06:37:12 -0800 (PST) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alex.bennee@linaro.org, serge.fdrv@gmail.com, rth@twiddle.net, qemu-arm@nongnu.org, edgar.iglesias@xilinx.com Subject: [PATCH v1 9/9] target-arm: Use isyn.swstep.ex to hold the is_ldex state Date: Fri, 12 Feb 2016 15:34:02 +0100 Message-Id: <1455287642-28166-10-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1455287642-28166-1-git-send-email-edgar.iglesias@gmail.com> References: <1455287642-28166-1-git-send-email-edgar.iglesias@gmail.com> X-TUID: o31lUVi+1UWx From: "Edgar E. Iglesias" Switch to using isyn.swstep.ex to hold the is_ldex state for SWStep syndrome generation. No functional change. Signed-off-by: Edgar E. Iglesias --- target-arm/translate-a64.c | 6 +++--- target-arm/translate.c | 6 +++--- target-arm/translate.h | 5 ----- 3 files changed, 6 insertions(+), 11 deletions(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 2f17cba..1d7fbcb 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -260,7 +260,7 @@ static void gen_step_complete_exception(DisasContext *s) * of the exception, and our syndrome information is always correct. */ gen_ss_advance(s); - gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex), + gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->isyn.swstep.ex), default_exception_el(s)); s->is_jmp = DISAS_EXC; } @@ -1865,7 +1865,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) if (is_excl) { if (!is_store) { - s->is_ldex = true; + s->isyn.swstep.ex = true; gen_load_exclusive(s, rt, rt2, tcg_addr, size, is_pair); } else { gen_store_exclusive(s, rs, rt, rt2, tcg_addr, size, is_pair); @@ -11127,7 +11127,7 @@ void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb) */ dc->ss_active = ARM_TBFLAG_SS_ACTIVE(tb->flags); dc->pstate_ss = ARM_TBFLAG_PSTATE_SS(tb->flags); - dc->is_ldex = false; + dc->isyn.swstep.ex = false; dc->ss_same_el = (arm_debug_target_el(env) == dc->current_el); init_tmp_a64_array(dc); diff --git a/target-arm/translate.c b/target-arm/translate.c index 0d53e7d..605d21b 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -250,7 +250,7 @@ static void gen_step_complete_exception(DisasContext *s) * of the exception, and our syndrome information is always correct. */ gen_ss_advance(s); - gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex), + gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->isyn.swstep.ex), default_exception_el(s)); s->is_jmp = DISAS_EXC; } @@ -7431,7 +7431,7 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2, { TCGv_i32 tmp = tcg_temp_new_i32(); - s->is_ldex = true; + s->isyn.swstep.ex = true; switch (size) { case 0: @@ -11284,7 +11284,7 @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb) */ dc->ss_active = ARM_TBFLAG_SS_ACTIVE(tb->flags); dc->pstate_ss = ARM_TBFLAG_PSTATE_SS(tb->flags); - dc->is_ldex = false; + dc->isyn.swstep.ex = false; dc->ss_same_el = false; /* Can't be true since EL_d must be AArch64 */ cpu_F0s = tcg_temp_new_i32(); diff --git a/target-arm/translate.h b/target-arm/translate.h index 2130a84..d500342 100644 --- a/target-arm/translate.h +++ b/target-arm/translate.h @@ -49,11 +49,6 @@ typedef struct DisasContext { */ bool ss_active; bool pstate_ss; - /* True if the insn just emitted was a load-exclusive instruction - * (necessary for syndrome information for single step exceptions), - * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*. - */ - bool is_ldex; /* True if a single-step exception will be taken to the current EL */ bool ss_same_el; /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ -- 1.9.1