From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
Sergey Fedorov <serge.fdrv@gmail.com>,
qemu-arm@nongnu.org, patches@linaro.org
Subject: [Qemu-devel] [PATCH 06/11] target-arm: Add comment about not implementing NSACR.RFR
Date: Mon, 15 Feb 2016 17:22:52 +0000 [thread overview]
Message-ID: <1455556977-3644-7-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1455556977-3644-1-git-send-email-peter.maydell@linaro.org>
QEMU doesn't implement the NSACR.RFR bit, which is a permitted
IMPDEF in choice in ARMv7 and the only permitted choice in ARMv8.
Add a comment to bad_mode_switch() to note that this is why
FIQ is always a valid mode regardless of the CPU's Secure state.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 9998a25..37b5439 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -5180,6 +5180,9 @@ static int bad_mode_switch(CPUARMState *env, int mode)
case ARM_CPU_MODE_UND:
case ARM_CPU_MODE_IRQ:
case ARM_CPU_MODE_FIQ:
+ /* Note that we don't implement the IMPDEF NSACR.RFR which in v7
+ * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
+ */
return 0;
case ARM_CPU_MODE_MON:
return !arm_is_secure(env);
--
1.9.1
next prev parent reply other threads:[~2016-02-15 17:27 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-15 17:22 [Qemu-devel] [PATCH 00/11] target-arm: clean up cpsr_write mode changing Peter Maydell
2016-02-15 17:22 ` [Qemu-arm] [PATCH 01/11] target-arm: Give CPSR setting on 32-bit exception return its own helper Peter Maydell
2016-02-18 17:41 ` Sergey Fedorov
2016-02-15 17:22 ` [Qemu-arm] [PATCH 02/11] target-arm: Add write_type argument to cpsr_write() Peter Maydell
2016-02-18 17:42 ` Sergey Fedorov
2016-02-15 17:22 ` [Qemu-devel] [PATCH 03/11] target-arm: Raw CPSR writes should skip checks and bank switching Peter Maydell
2016-02-18 17:42 ` [Qemu-arm] " Sergey Fedorov
2016-02-15 17:22 ` [Qemu-arm] [PATCH 04/11] linux-user: Use restrictive mask when calling cpsr_write() Peter Maydell
2016-02-18 17:42 ` [Qemu-devel] " Sergey Fedorov
2016-02-15 17:22 ` [Qemu-arm] [PATCH 05/11] target-arm: In cpsr_write() ignore mode switches from User mode Peter Maydell
2016-02-18 17:43 ` Sergey Fedorov
2016-02-15 17:22 ` Peter Maydell [this message]
2016-02-18 17:43 ` [Qemu-devel] [PATCH 06/11] target-arm: Add comment about not implementing NSACR.RFR Sergey Fedorov
2016-02-15 17:22 ` [Qemu-devel] [PATCH 07/11] target-arm: Add Hyp mode checks to bad_mode_switch() Peter Maydell
2016-02-18 17:43 ` [Qemu-arm] " Sergey Fedorov
2016-02-15 17:22 ` [Qemu-devel] [PATCH 08/11] target-arm: Forbid mode switch to Mon from Secure EL1 Peter Maydell
2016-02-18 17:43 ` [Qemu-arm] " Sergey Fedorov
2016-02-15 17:22 ` [Qemu-devel] [PATCH 09/11] target-arm: In v8, make illegal AArch32 mode changes set PSTATE.IL Peter Maydell
2016-02-18 17:44 ` [Qemu-arm] " Sergey Fedorov
2016-02-15 17:22 ` [Qemu-devel] [PATCH 10/11] target-arm: Make mode switches from Hyp via CPS and MRS illegal Peter Maydell
2016-02-18 17:44 ` [Qemu-arm] " Sergey Fedorov
2016-02-15 17:22 ` [Qemu-devel] [PATCH 11/11] target-arm: Make Monitor->NS PL1 mode changes illegal if HCR.TGE is 1 Peter Maydell
2016-02-18 17:44 ` [Qemu-arm] " Sergey Fedorov
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