From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
Sergey Fedorov <serge.fdrv@gmail.com>,
qemu-arm@nongnu.org, patches@linaro.org
Subject: [Qemu-devel] [PATCH v2 0/2] Implement MDCR_EL3.TPM and MDCR_EL2.TPM traps
Date: Fri, 19 Feb 2016 14:39:42 +0000 [thread overview]
Message-ID: <1455892784-11328-1-git-send-email-peter.maydell@linaro.org> (raw)
This patchset implements the MDCR_EL3 and MDCR_EL2 trap bits
to trap the performance monitor registers.
Patch 2 is the same as I sent out earlier today as a standalone
patch. Patch 1 fixes a couple of bugs in our SDCR handling, and
in particular imposes a mask so that if a guest has booted with
EL3 in AArch32 then it cannot set bits like TPM which are RES0
for the 32-bit version of the register.
Peter Maydell (2):
target-arm: Fix handling of SDCR for 32-bit code
target-arm: Implement MDCR_EL3.TPM and MDCR_EL2.TPM traps
target-arm/cpu.h | 4 ++++
target-arm/helper.c | 66 +++++++++++++++++++++++++++++++++++++++++------------
2 files changed, 55 insertions(+), 15 deletions(-)
--
1.9.1
next reply other threads:[~2016-02-19 14:40 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-19 14:39 Peter Maydell [this message]
2016-02-19 14:39 ` [Qemu-devel] [PATCH v2 1/2] target-arm: Fix handling of SDCR for 32-bit code Peter Maydell
2016-02-19 16:31 ` [Qemu-arm] " Sergey Fedorov
2016-02-19 16:38 ` Peter Maydell
2016-02-22 18:08 ` [Qemu-arm] [Qemu-devel] " Alistair Francis
2016-02-19 14:39 ` [Qemu-devel] [PATCH v2 2/2] target-arm: Implement MDCR_EL3.TPM and MDCR_EL2.TPM traps Peter Maydell
2016-02-19 16:42 ` [Qemu-arm] " Sergey Fedorov
2016-02-19 19:38 ` [Qemu-arm] [Qemu-devel] " Alistair Francis
2016-02-20 11:28 ` Peter Maydell
2016-02-22 18:06 ` Alistair Francis
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