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[52.8.89.49]) by smtp.gmail.com with ESMTPSA id r5sm19840740pap.7.2016.02.19.12.05.15 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Fri, 19 Feb 2016 12:05:15 -0800 (PST) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alex.bennee@linaro.org, serge.fdrv@gmail.com, rth@twiddle.net, qemu-arm@nongnu.org, edgar.iglesias@xilinx.com Subject: [PATCH v2 4/8] target-arm: Add more fields to the data abort syndrome generator Date: Fri, 19 Feb 2016 21:04:48 +0100 Message-Id: <1455912292-23807-5-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1455912292-23807-1-git-send-email-edgar.iglesias@gmail.com> References: <1455912292-23807-1-git-send-email-edgar.iglesias@gmail.com> X-TUID: IT/b8lAoxFtM From: "Edgar E. Iglesias" Add the following flags to the data abort syndrome generator: * isv - Instruction syndrome valid * sas - Syndrome access size * sse - Syndrome sign extend * srt - Syndrome register transfer * sf - Sixty-Four bit register width * ar - Acquire/Release These flags are not yet used, so this patch has no functional change. Signed-off-by: Edgar E. Iglesias --- target-arm/internals.h | 20 ++++++++++++++++++-- target-arm/op_helper.c | 8 ++++++-- 2 files changed, 24 insertions(+), 4 deletions(-) diff --git a/target-arm/internals.h b/target-arm/internals.h index 34e2688..4e9d9f5 100644 --- a/target-arm/internals.h +++ b/target-arm/internals.h @@ -383,13 +383,29 @@ static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc) | (ea << 9) | (s1ptw << 7) | fsc; } -static inline uint32_t syn_data_abort(int same_el, int ea, int cm, int s1ptw, +static inline uint32_t syn_data_abort(int same_el, int isv, + int sas, int sse, int srt, + int sf, int ar, + int ea, int cm, int s1ptw, int wnr, int fsc, bool is_16bit) { - return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) + uint32_t v; + v = (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) | (is_16bit ? 0 : ARM_EL_IL) | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc; + + /* Insn Syndrome fields are RES0 if ISV is unset. */ + if (isv) { + v |= (isv << 24) | (sas << 22) | (sse << 21) | (srt << 16) + | (sf << 15) | (ar << 14); + } else { + /* If ISV is zero, the IL field should be set to one. + * See ARM ARMv8 D7.2.27 for more details. + */ + v |= ARM_EL_IL; + } + return v; } static inline uint32_t syn_swstep(int same_el, int isv, int ex) diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index 7e845d5..2522d3c 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -115,7 +115,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, syn = syn_insn_abort(same_el, 0, fi.s1ptw, syn); exc = EXCP_PREFETCH_ABORT; } else { - syn = syn_data_abort(same_el, 0, 0, fi.s1ptw, is_write == 1, syn, + syn = syn_data_abort(same_el, + 0, 0, 0, 0, 0, 0, + 0, 0, fi.s1ptw, is_write == 1, syn, 1); if (is_write == 1 && arm_feature(env, ARM_FEATURE_V6)) { fsr |= (1 << 11); @@ -162,7 +164,9 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, int is_write, } raise_exception(env, EXCP_DATA_ABORT, - syn_data_abort(same_el, 0, 0, 0, is_write == 1, 0x21, + syn_data_abort(same_el, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, is_write == 1, 0x21, 1), target_el); } -- 1.9.1