From: "Cédric Le Goater" <clg@kaod.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: "Jan Kiszka" <jan.kiszka@siemens.com>,
"Jason Wang" <jasowang@redhat.com>,
qemu-devel@nongnu.org, qemu-arm@nongnu.org,
"Cédric Le Goater" <clg@kaod.org>,
"Dmitry Fleytman" <dmitry@daynix.com>,
"Samuel Thibault" <samuel.thibault@ens-lyon.org>
Subject: [Qemu-arm] [RFC PATCH 2/4] net/ftgmac100: add a 'aspeed' property
Date: Tue, 29 Nov 2016 18:42:01 +0100 [thread overview]
Message-ID: <1480441323-31417-3-git-send-email-clg@kaod.org> (raw)
In-Reply-To: <1480441323-31417-1-git-send-email-clg@kaod.org>
The Aspeed SoCs have a different definition of the end of the ring
buffer bit. Add a property to specify which set of bits should be used
by the NIC.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
---
hw/net/ftgmac100.c | 19 +++++++++++++++----
include/hw/net/ftgmac100.h | 3 +++
2 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c
index 4a7f865f226b..fceeffcb7a7f 100644
--- a/hw/net/ftgmac100.c
+++ b/hw/net/ftgmac100.c
@@ -112,6 +112,7 @@ struct ftgmac100_txdes {
#define FTGMAC100_TXDES0_CRC_ERR (1 << 19)
#define FTGMAC100_TXDES0_LTS (1 << 28)
#define FTGMAC100_TXDES0_FTS (1 << 29)
+#define FTGMAC100_TXDES0_EDOTR_ASPEED (1 << 30)
#define FTGMAC100_TXDES0_TXDMA_OWN (1 << 31)
#define FTGMAC100_TXDES1_VLANTAG_CI(x) ((x) & 0xffff)
@@ -147,6 +148,7 @@ struct ftgmac100_rxdes {
#define FTGMAC100_RXDES0_PAUSE_FRAME (1 << 25)
#define FTGMAC100_RXDES0_LRS (1 << 28)
#define FTGMAC100_RXDES0_FRS (1 << 29)
+#define FTGMAC100_RXDES0_EDORR_ASPEED (1 << 30)
#define FTGMAC100_RXDES0_RXPKT_RDY (1 << 31)
#define FTGMAC100_RXDES1_VLANTAG_CI 0xffff
@@ -373,7 +375,7 @@ static uint32_t ftgmac100_find_txdes(Ftgmac100State *s, uint32_t addr)
while (1) {
ftgmac100_read_bd(&bd, addr);
- if (bd.des0 & (FTGMAC100_TXDES0_FTS | FTGMAC100_TXDES0_EDOTR)) {
+ if (bd.des0 & (FTGMAC100_TXDES0_FTS | s->txdes0_edotr)) {
break;
}
addr += sizeof(Ftgmac100Desc);
@@ -427,7 +429,7 @@ static void ftgmac100_do_tx(Ftgmac100State *s)
/* Write back the modified descriptor. */
ftgmac100_write_bd(&bd, addr);
/* Advance to the next descriptor. */
- if (bd.des0 & FTGMAC100_TXDES0_EDOTR) {
+ if (bd.des0 & s->txdes0_edotr) {
addr = s->tx_ring;
} else {
addr += sizeof(Ftgmac100Desc);
@@ -448,7 +450,7 @@ static void ftgmac100_enable_rx(Ftgmac100State *s)
while (1) {
ftgmac100_read_bd(&bd, s->rx_descriptor);
full = (bd.des0 & FTGMAC100_RXDES0_RXPKT_RDY);
- if (!full || bd.des0 & FTGMAC100_TXDES0_EDOTR) {
+ if (!full || bd.des0 & s->txdes0_edotr) {
break;
}
s->rx_descriptor += sizeof(Ftgmac100Desc);
@@ -739,7 +741,7 @@ static ssize_t ftgmac100_receive(NetClientState *nc, const uint8_t *buf,
s->isr |= FTGMAC100_INT_RPKT_FIFO;
}
ftgmac100_write_bd(&bd, addr);
- if (bd.des0 & FTGMAC100_RXDES0_EDORR) {
+ if (bd.des0 & s->rxdes0_edorr) {
addr = s->rx_ring;
} else {
addr += sizeof(Ftgmac100Desc);
@@ -781,6 +783,14 @@ static void ftgmac100_realize(DeviceState *dev, Error **errp)
Ftgmac100State *s = FTGMAC100(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+ if (s->aspeed) {
+ s->txdes0_edotr = FTGMAC100_TXDES0_EDOTR_ASPEED;
+ s->rxdes0_edorr = FTGMAC100_RXDES0_EDORR_ASPEED;
+ } else {
+ s->txdes0_edotr = FTGMAC100_TXDES0_EDOTR;
+ s->rxdes0_edorr = FTGMAC100_RXDES0_EDORR;
+ }
+
memory_region_init_io(&s->iomem, OBJECT(dev), &ftgmac100_ops, s,
TYPE_FTGMAC100, 0x2000);
sysbus_init_mmio(sbd, &s->iomem);
@@ -824,6 +834,7 @@ static const VMStateDescription vmstate_ftgmac100 = {
};
static Property ftgmac100_properties[] = {
+ DEFINE_PROP_BOOL("aspeed", Ftgmac100State, aspeed, false),
DEFINE_NIC_PROPERTIES(Ftgmac100State, conf),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/include/hw/net/ftgmac100.h b/include/hw/net/ftgmac100.h
index 1aa22de9e450..7476011f0657 100644
--- a/include/hw/net/ftgmac100.h
+++ b/include/hw/net/ftgmac100.h
@@ -46,6 +46,9 @@ typedef struct Ftgmac100State {
uint32_t phy_int;
uint32_t phy_int_mask;
+ bool aspeed;
+ uint32_t txdes0_edotr;
+ uint32_t rxdes0_edorr;
} Ftgmac100State;
#endif
--
2.7.4
next prev parent reply other threads:[~2016-11-29 17:42 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-29 17:41 [Qemu-devel] [RFC PATCH 0/4] FTGMAC100 model for the Aspeed SoCs Cédric Le Goater
2016-11-29 17:42 ` [Qemu-arm] [RFC PATCH 1/4] net: add FTGMAC100 support Cédric Le Goater
2016-11-29 17:42 ` Cédric Le Goater [this message]
2016-11-29 17:42 ` [Qemu-devel] [RFC PATCH 3/4] aspeed: add a FTGMAC100 nic Cédric Le Goater
2016-11-29 17:42 ` [Qemu-devel] [RFC PATCH 4/4] slirp: add a fake NC-SI backend Cédric Le Goater
2016-12-16 16:48 ` [Qemu-arm] [RFC PATCH 0/4] FTGMAC100 model for the Aspeed SoCs Peter Maydell
2016-12-16 17:24 ` Cédric Le Goater
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