From mboxrd@z Thu Jan 1 00:00:00 1970 Received: by 10.25.150.194 with SMTP id y185csp2471520lfd; Tue, 29 Nov 2016 09:44:47 -0800 (PST) X-Received: by 10.200.48.207 with SMTP id w15mr25217082qta.171.1480441487194; Tue, 29 Nov 2016 09:44:47 -0800 (PST) Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id r186si35439523qkc.41.2016.11.29.09.44.46 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 29 Nov 2016 09:44:47 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+alex.bennee=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+alex.bennee=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+alex.bennee=linaro.org@nongnu.org Received: from localhost ([::1]:38450 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cBmST-00006s-U6 for alex.bennee@linaro.org; Tue, 29 Nov 2016 12:44:45 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47063) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cBmQY-0007Sm-Cw for qemu-devel@nongnu.org; Tue, 29 Nov 2016 12:42:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cBmQU-0001VA-9x for qemu-devel@nongnu.org; Tue, 29 Nov 2016 12:42:46 -0500 Received: from mo69.mail-out.ovh.net ([178.32.228.69]:36417) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cBmQU-0001UC-3c for qemu-devel@nongnu.org; Tue, 29 Nov 2016 12:42:42 -0500 Received: from player699.ha.ovh.net (b9.ovh.net [213.186.33.59]) by mo69.mail-out.ovh.net (Postfix) with ESMTP id 127B6CE40 for ; Tue, 29 Nov 2016 18:42:41 +0100 (CET) Received: from hermes.kaod.org.com (LFbn-1-2234-107.w90-76.abo.wanadoo.fr [90.76.55.107]) (Authenticated sender: clg@kaod.org) by player699.ha.ovh.net (Postfix) with ESMTPSA id AEF1624006E; Tue, 29 Nov 2016 18:42:32 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: Peter Maydell Date: Tue, 29 Nov 2016 18:42:02 +0100 Message-Id: <1480441323-31417-4-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1480441323-31417-1-git-send-email-clg@kaod.org> References: <1480441323-31417-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 X-Ovh-Tracer-Id: 13695727944663272209 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelfedrfeejgddvfeegucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 178.32.228.69 Subject: [Qemu-devel] [RFC PATCH 3/4] aspeed: add a FTGMAC100 nic X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jan Kiszka , Jason Wang , qemu-devel@nongnu.org, qemu-arm@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Dmitry Fleytman , Samuel Thibault Errors-To: qemu-devel-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-devel" X-TUID: Nnn84tSSd7Bj There is a second NIC but we do not use it for the moment. We use the 'aspeed' property to tune the definition of the end of ring buffer bit for the Aspeed SoCs. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Joel Stanley Reviewed-by: Andrew Jeffery --- hw/arm/aspeed_soc.c | 21 +++++++++++++++++++++ include/hw/arm/aspeed_soc.h | 2 ++ 2 files changed, 23 insertions(+) diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 712ae9d6c54d..af0964cf6add 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -19,6 +19,7 @@ #include "hw/char/serial.h" #include "qemu/log.h" #include "hw/i2c/aspeed_i2c.h" +#include "net/net.h" =20 #define ASPEED_SOC_UART_5_BASE 0x00184000 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 @@ -33,6 +34,8 @@ #define ASPEED_SOC_TIMER_BASE 0x1E782000 #define ASPEED_SOC_WDT_BASE 0x1E785000 #define ASPEED_SOC_I2C_BASE 0x1E78A000 +#define ASPEED_SOC_ETH1_BASE 0x1E660000 +#define ASPEED_SOC_ETH2_BASE 0x1E680000 =20 static const int uart_irqs[] =3D { 9, 32, 33, 34, 10 }; static const int timer_irqs[] =3D { 16, 17, 18, 35, 36, 37, 38, 39, }; @@ -177,6 +180,10 @@ static void aspeed_soc_init(Object *obj) qdev_set_parent_bus(DEVICE(&s->wdt), sysbus_get_default()); object_property_add_const_link(OBJECT(&s->wdt), "scu", OBJECT(&s->sc= u), NULL); + + object_initialize(&s->ftgmac100, sizeof(s->ftgmac100), TYPE_FTGMAC10= 0); + object_property_add_child(obj, "ftgmac100", OBJECT(&s->ftgmac100), N= ULL); + qdev_set_parent_bus(DEVICE(&s->ftgmac100), sysbus_get_default()); } =20 static void aspeed_soc_realize(DeviceState *dev, Error **errp) @@ -304,6 +311,20 @@ static void aspeed_soc_realize(DeviceState *dev, Err= or **errp) return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, ASPEED_SOC_WDT_BASE); + + /* Net */ + qdev_set_nic_properties(DEVICE(&s->ftgmac100), &nd_table[0]); + object_property_set_bool(OBJECT(&s->ftgmac100), true, "aspeed", &err= ); + object_property_set_bool(OBJECT(&s->ftgmac100), true, "realized", + &local_err); + error_propagate(&err, local_err); + if (err) { + error_propagate(errp, err); + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100), 0, ASPEED_SOC_ETH1_BA= SE); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100), 0, + qdev_get_gpio_in(DEVICE(&s->vic), 2)); } =20 static void aspeed_soc_class_init(ObjectClass *oc, void *data) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index dbec0c159885..1fd0dc690be1 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -20,6 +20,7 @@ #include "hw/i2c/aspeed_i2c.h" #include "hw/ssi/aspeed_smc.h" #include "hw/watchdog/wdt_aspeed.h" +#include "hw/net/ftgmac100.h" =20 #define ASPEED_SPIS_NUM 2 =20 @@ -39,6 +40,7 @@ typedef struct AspeedSoCState { AspeedSMCState spi[ASPEED_SPIS_NUM]; AspeedSDMCState sdmc; AspeedWDTState wdt; + Ftgmac100State ftgmac100; } AspeedSoCState; =20 #define TYPE_ASPEED_SOC "aspeed-soc" --=20 2.7.4