From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: Andrew Jones <drjones@redhat.com>,
Christoffer Dall <christoffer.dall@linaro.org>,
patches@linaro.org
Subject: [Qemu-arm] [PATCH 01/23] target-arm: Log AArch64 exception returns
Date: Tue, 13 Dec 2016 10:36:02 +0000 [thread overview]
Message-ID: <1481625384-15077-2-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1481625384-15077-1-git-send-email-peter.maydell@linaro.org>
We already log exception entry; add logging of the AArch64 exception
return path as well.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
target-arm/op_helper.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index cd94216..ba796d8 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -17,6 +17,7 @@
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
+#include "qemu/log.h"
#include "cpu.h"
#include "exec/helper-proto.h"
#include "internals.h"
@@ -972,6 +973,9 @@ void HELPER(exception_return)(CPUARMState *env)
} else {
env->regs[15] = env->elr_el[cur_el] & ~0x3;
}
+ qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to "
+ "AArch32 EL%d PC 0x%" PRIx32 "\n",
+ cur_el, new_el, env->regs[15]);
} else {
env->aarch64 = 1;
pstate_write(env, spsr);
@@ -980,6 +984,9 @@ void HELPER(exception_return)(CPUARMState *env)
}
aarch64_restore_sp(env, new_el);
env->pc = env->elr_el[cur_el];
+ qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to "
+ "AArch64 EL%d PC 0x%" PRIx64 "\n",
+ cur_el, new_el, env->pc);
}
arm_call_el_change_hook(arm_env_get_cpu(env));
@@ -1002,6 +1009,8 @@ illegal_return:
if (!arm_singlestep_active(env)) {
env->pstate &= ~PSTATE_SS;
}
+ qemu_log_mask(LOG_GUEST_ERROR, "Illegal exception return at EL%d: "
+ "resuming execution at 0x%" PRIx64 "\n", cur_el, env->pc);
}
/* Return true if the linked breakpoint entry lbn passes its checks */
--
2.7.4
next prev parent reply other threads:[~2016-12-13 11:04 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-12-13 10:36 [Qemu-arm] [PATCH 00/23] arm: Add virtualization to GICv3, and enable EL2 on 64-bit CPUs Peter Maydell
2016-12-13 10:36 ` Peter Maydell [this message]
2016-12-19 21:51 ` [Qemu-arm] [Qemu-devel] [PATCH 01/23] target-arm: Log AArch64 exception returns Alistair Francis
2016-12-20 15:31 ` Andrew Jones
2016-12-27 15:13 ` Peter Maydell
2016-12-13 10:36 ` [Qemu-arm] [PATCH 02/23] hw/intc/arm_gicv3: Remove incorrect usage of fieldoffset Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 03/23] hw/intc/arm_gicv3: Don't signal Pending+Active interrupts to CPU Peter Maydell
2016-12-13 10:36 ` [Qemu-arm] [PATCH 04/23] hw/arm/virt: add 2.9 machine type Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 05/23] hw/arm/virt: Merge VirtBoardInfo and VirtMachineState Peter Maydell
2016-12-13 10:36 ` [Qemu-arm] [PATCH 06/23] hw/arm/virt: Rename 'vbi' variables to 'vms' Peter Maydell
2016-12-20 15:46 ` [Qemu-arm] [Qemu-devel] " Andrew Jones
2016-12-13 10:36 ` [Qemu-arm] [PATCH 07/23] hw/arm/virt: Don't incorrectly claim architectural timer to be edge-triggered Peter Maydell
2016-12-13 10:36 ` [Qemu-arm] [PATCH 08/23] hw/intc/arm_gicv3: Add external IRQ lines for VIRQ and VFIQ Peter Maydell
2016-12-13 10:36 ` [Qemu-arm] [PATCH 09/23] hw/intc/arm_gic: " Peter Maydell
2016-12-19 21:54 ` [Qemu-arm] [Qemu-devel] " Alistair Francis
2016-12-13 10:36 ` [Qemu-arm] [PATCH 10/23] target-arm: Expose output GPIO line for VCPU maintenance interrupt Peter Maydell
2016-12-13 12:37 ` Edgar E. Iglesias
2016-12-13 10:36 ` [Qemu-arm] [PATCH 11/23] hw/arm/virt: Wire VIRQ, VFIQ, maintenance irq lines from GIC to CPU Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 12/23] target-arm: Add ARMCPU fields for GIC CPU i/f config Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 13/23] hw/intc/gicv3: Add defines for ICH system register fields Peter Maydell
2016-12-13 10:36 ` [Qemu-arm] [PATCH 14/23] hw/intc/gicv3: Add data fields for virtualization support Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 15/23] hw/intc/arm_gicv3: Add accessors for ICH_ system registers Peter Maydell
2016-12-13 10:36 ` [Qemu-arm] [PATCH 16/23] hw/intc/arm_gicv3: Implement ICV_ registers which are just accessors Peter Maydell
2016-12-13 10:36 ` [Qemu-arm] [PATCH 17/23] hw/intc/arm_gicv3: Implement ICV_ HPPIR, DIR and RPR registers Peter Maydell
2016-12-13 10:36 ` [Qemu-arm] [PATCH 18/23] hw/intc/arm_gicv3: Implement ICV_ registers EOIR and IAR Peter Maydell
2016-12-13 10:36 ` [Qemu-arm] [PATCH 19/23] hw/intc/arm_gicv3: Implement gicv3_cpuif_virt_update() Peter Maydell
2016-12-13 10:36 ` [Qemu-arm] [PATCH 20/23] hw/intc/arm_gicv3: Implement EL2 traps for CPU i/f regs Peter Maydell
2016-12-13 10:36 ` [Qemu-arm] [PATCH 21/23] hw/arm/virt: Support using SMC for PSCI Peter Maydell
2016-12-13 12:36 ` Edgar E. Iglesias
2016-12-28 13:14 ` [Qemu-arm] [Qemu-devel] " Andrew Jones
2016-12-13 10:36 ` [Qemu-arm] [PATCH 22/23] target-arm: Enable EL2 feature bit on A53 and A57 Peter Maydell
2016-12-13 16:11 ` Edgar E. Iglesias
2016-12-19 22:04 ` [Qemu-arm] [Qemu-devel] " Alistair Francis
2016-12-20 13:32 ` Peter Maydell
2016-12-20 17:46 ` Alistair Francis
2016-12-28 13:14 ` Andrew Jones
2016-12-13 10:36 ` [Qemu-arm] [PATCH 23/23] hw/arm/virt: Add board property to enable EL2 Peter Maydell
2016-12-28 13:14 ` [Qemu-arm] [Qemu-devel] " Andrew Jones
2017-01-17 22:15 ` Alistair Francis
2016-12-13 21:16 ` [Qemu-arm] [Qemu-devel] [PATCH 00/23] arm: Add virtualization to GICv3, and enable EL2 on 64-bit CPUs Andrew Jones
2016-12-14 10:18 ` Peter Maydell
2017-01-09 15:08 ` Peter Maydell
2016-12-16 21:42 ` [Qemu-arm] " Andrew Jones
2016-12-19 22:20 ` [Qemu-arm] [Qemu-devel] " Alistair Francis
2017-01-09 15:57 ` Peter Maydell
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