* [Qemu-arm] [PATCH v3 1/7] arm: Uniquely name imx25 I2C buses.
2016-12-02 5:46 [Qemu-arm] [PATCH v3 0/7] Add support for the Epson RX8900 RTC to the aspeed board Alastair D'Silva
@ 2016-12-02 5:46 ` Alastair D'Silva
2016-12-14 17:41 ` Peter Maydell
2016-12-02 5:46 ` [Qemu-devel] [PATCH v3 2/7] hw/arm: remove trailing whitespace Alastair D'Silva
` (5 subsequent siblings)
6 siblings, 1 reply; 16+ messages in thread
From: Alastair D'Silva @ 2016-12-02 5:46 UTC (permalink / raw)
To: qemu-arm
Cc: Peter Maydell, Andrew Jeffery, qemu-devel, Joel Stanley,
Alastair D'Silva, Cédric Le Goater
From: Alastair D'Silva <alastair@d-silva.org>
The imx25 chip provides 3 i2c buses, but they have all been named
"i2c", which makes it difficult to predict which bus a device will
be connected to when specified on the command line.
This patch addresses the issue by naming the buses uniquely:
i2c-bus.0 i2c-bus.1 i2c-bus.2
Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
---
hw/arm/imx25_pdk.c | 4 +---
hw/i2c/imx_i2c.c | 2 +-
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c
index 025b608..c6f04d3 100644
--- a/hw/arm/imx25_pdk.c
+++ b/hw/arm/imx25_pdk.c
@@ -138,9 +138,7 @@ static void imx25_pdk_init(MachineState *machine)
* We add it here (only on qtest usage) to be able to do a bit
* of simple qtest. See "make check" for details.
*/
- i2c_create_slave((I2CBus *)qdev_get_child_bus(DEVICE(&s->soc.i2c[0]),
- "i2c"),
- "ds1338", 0x68);
+ i2c_create_slave(s->soc.i2c[0].bus, "ds1338", 0x68);
}
}
diff --git a/hw/i2c/imx_i2c.c b/hw/i2c/imx_i2c.c
index 37e5a62..6c81b98 100644
--- a/hw/i2c/imx_i2c.c
+++ b/hw/i2c/imx_i2c.c
@@ -310,7 +310,7 @@ static void imx_i2c_realize(DeviceState *dev, Error **errp)
IMX_I2C_MEM_SIZE);
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
- s->bus = i2c_init_bus(DEVICE(dev), "i2c");
+ s->bus = i2c_init_bus(DEVICE(dev), NULL);
}
static void imx_i2c_class_init(ObjectClass *klass, void *data)
--
2.9.3
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [Qemu-arm] [PATCH v3 1/7] arm: Uniquely name imx25 I2C buses.
2016-12-02 5:46 ` [Qemu-arm] [PATCH v3 1/7] arm: Uniquely name imx25 I2C buses Alastair D'Silva
@ 2016-12-14 17:41 ` Peter Maydell
2016-12-14 17:54 ` Cédric Le Goater
0 siblings, 1 reply; 16+ messages in thread
From: Peter Maydell @ 2016-12-14 17:41 UTC (permalink / raw)
To: Alastair D'Silva
Cc: Andrew Jeffery, QEMU Developers, qemu-arm, Joel Stanley,
Alastair D'Silva, Cédric Le Goater
On 2 December 2016 at 05:46, Alastair D'Silva <alastair@au1.ibm.com> wrote:
> From: Alastair D'Silva <alastair@d-silva.org>
>
> The imx25 chip provides 3 i2c buses, but they have all been named
> "i2c", which makes it difficult to predict which bus a device will
> be connected to when specified on the command line.
>
> This patch addresses the issue by naming the buses uniquely:
> i2c-bus.0 i2c-bus.1 i2c-bus.2
>
> Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
> ---
> hw/arm/imx25_pdk.c | 4 +---
> hw/i2c/imx_i2c.c | 2 +-
> 2 files changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c
> index 025b608..c6f04d3 100644
> --- a/hw/arm/imx25_pdk.c
> +++ b/hw/arm/imx25_pdk.c
> @@ -138,9 +138,7 @@ static void imx25_pdk_init(MachineState *machine)
> * We add it here (only on qtest usage) to be able to do a bit
> * of simple qtest. See "make check" for details.
> */
> - i2c_create_slave((I2CBus *)qdev_get_child_bus(DEVICE(&s->soc.i2c[0]),
> - "i2c"),
> - "ds1338", 0x68);
> + i2c_create_slave(s->soc.i2c[0].bus, "ds1338", 0x68);
This bit doesn't look right. The board level code shouldn't be
poking around inside the IMXI2CState struct, as that is private
to the device implementation. That's why we're calling
qdev_get_child_bus().
> }
> }
thanks
-- PMM
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Qemu-arm] [PATCH v3 1/7] arm: Uniquely name imx25 I2C buses.
2016-12-14 17:41 ` Peter Maydell
@ 2016-12-14 17:54 ` Cédric Le Goater
0 siblings, 0 replies; 16+ messages in thread
From: Cédric Le Goater @ 2016-12-14 17:54 UTC (permalink / raw)
To: Peter Maydell, Alastair D'Silva
Cc: Andrew Jeffery, qemu-arm, Alastair D'Silva, QEMU Developers,
Joel Stanley
On 12/14/2016 06:41 PM, Peter Maydell wrote:
> On 2 December 2016 at 05:46, Alastair D'Silva <alastair@au1.ibm.com> wrote:
>> From: Alastair D'Silva <alastair@d-silva.org>
>>
>> The imx25 chip provides 3 i2c buses, but they have all been named
>> "i2c", which makes it difficult to predict which bus a device will
>> be connected to when specified on the command line.
>>
>> This patch addresses the issue by naming the buses uniquely:
>> i2c-bus.0 i2c-bus.1 i2c-bus.2
>>
>> Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
>> ---
>> hw/arm/imx25_pdk.c | 4 +---
>> hw/i2c/imx_i2c.c | 2 +-
>> 2 files changed, 2 insertions(+), 4 deletions(-)
>>
>> diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c
>> index 025b608..c6f04d3 100644
>> --- a/hw/arm/imx25_pdk.c
>> +++ b/hw/arm/imx25_pdk.c
>> @@ -138,9 +138,7 @@ static void imx25_pdk_init(MachineState *machine)
>> * We add it here (only on qtest usage) to be able to do a bit
>> * of simple qtest. See "make check" for details.
>> */
>> - i2c_create_slave((I2CBus *)qdev_get_child_bus(DEVICE(&s->soc.i2c[0]),
>> - "i2c"),
>> - "ds1338", 0x68);
>> + i2c_create_slave(s->soc.i2c[0].bus, "ds1338", 0x68);
>
> This bit doesn't look right. The board level code shouldn't be
> poking around inside the IMXI2CState struct, as that is private
> to the device implementation. That's why we're calling
> qdev_get_child_bus().
That was my suggestion. Sorry about that.
May be, we could use "i2c.0", now that we have numbered the I2C bus
names ?
Thanks,
C.
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH v3 2/7] hw/arm: remove trailing whitespace
2016-12-02 5:46 [Qemu-arm] [PATCH v3 0/7] Add support for the Epson RX8900 RTC to the aspeed board Alastair D'Silva
2016-12-02 5:46 ` [Qemu-arm] [PATCH v3 1/7] arm: Uniquely name imx25 I2C buses Alastair D'Silva
@ 2016-12-02 5:46 ` Alastair D'Silva
2016-12-14 18:05 ` Peter Maydell
2016-12-02 5:46 ` [Qemu-devel] [PATCH v3 3/7] hw/i2c: Add a NULL check for i2c slave init callbacks Alastair D'Silva
` (4 subsequent siblings)
6 siblings, 1 reply; 16+ messages in thread
From: Alastair D'Silva @ 2016-12-02 5:46 UTC (permalink / raw)
To: qemu-arm
Cc: Peter Maydell, Andrew Jeffery, qemu-devel, Joel Stanley,
Alastair D'Silva, Cédric Le Goater
From: Alastair D'Silva <alastair@d-silva.org>
Remove trailing whitespace in hw/arm/pxa2xx.c
Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
---
hw/arm/pxa2xx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
index 21ea1d6..8aa0f8a 100644
--- a/hw/arm/pxa2xx.c
+++ b/hw/arm/pxa2xx.c
@@ -2070,7 +2070,7 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space,
}
if (!revision)
revision = "pxa270";
-
+
s->cpu = cpu_arm_init(revision);
if (s->cpu == NULL) {
fprintf(stderr, "Unable to find CPU definition\n");
--
2.9.3
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [Qemu-devel] [PATCH v3 2/7] hw/arm: remove trailing whitespace
2016-12-02 5:46 ` [Qemu-devel] [PATCH v3 2/7] hw/arm: remove trailing whitespace Alastair D'Silva
@ 2016-12-14 18:05 ` Peter Maydell
0 siblings, 0 replies; 16+ messages in thread
From: Peter Maydell @ 2016-12-14 18:05 UTC (permalink / raw)
To: Alastair D'Silva
Cc: Andrew Jeffery, QEMU Developers, qemu-arm, Joel Stanley,
Alastair D'Silva, Cédric Le Goater
On 2 December 2016 at 05:46, Alastair D'Silva <alastair@au1.ibm.com> wrote:
> From: Alastair D'Silva <alastair@d-silva.org>
>
> Remove trailing whitespace in hw/arm/pxa2xx.c
>
> Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
> ---
> hw/arm/pxa2xx.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
> index 21ea1d6..8aa0f8a 100644
> --- a/hw/arm/pxa2xx.c
> +++ b/hw/arm/pxa2xx.c
> @@ -2070,7 +2070,7 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space,
> }
> if (!revision)
> revision = "pxa270";
> -
> +
> s->cpu = cpu_arm_init(revision);
> if (s->cpu == NULL) {
> fprintf(stderr, "Unable to find CPU definition\n");
> --
Applied this patch to target-arm.next for 2.9.
thanks
-- PMM
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH v3 3/7] hw/i2c: Add a NULL check for i2c slave init callbacks
2016-12-02 5:46 [Qemu-arm] [PATCH v3 0/7] Add support for the Epson RX8900 RTC to the aspeed board Alastair D'Silva
2016-12-02 5:46 ` [Qemu-arm] [PATCH v3 1/7] arm: Uniquely name imx25 I2C buses Alastair D'Silva
2016-12-02 5:46 ` [Qemu-devel] [PATCH v3 2/7] hw/arm: remove trailing whitespace Alastair D'Silva
@ 2016-12-02 5:46 ` Alastair D'Silva
2016-12-14 18:05 ` [Qemu-arm] " Peter Maydell
2016-12-02 5:46 ` [Qemu-devel] [PATCH v3 4/7] qtest: Support named interrupts Alastair D'Silva
` (3 subsequent siblings)
6 siblings, 1 reply; 16+ messages in thread
From: Alastair D'Silva @ 2016-12-02 5:46 UTC (permalink / raw)
To: qemu-arm
Cc: Peter Maydell, Andrew Jeffery, qemu-devel, Joel Stanley,
Alastair D'Silva, Cédric Le Goater
From: Alastair D'Silva <alastair@d-silva.org>
Add a NULL check for i2c slave init callbacks, so that we no longer need to implement empty init functions.
Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
---
hw/arm/pxa2xx.c | 7 -------
hw/arm/tosa.c | 7 -------
hw/arm/z2.c | 7 -------
hw/i2c/core.c | 6 +++++-
hw/timer/ds1338.c | 6 ------
5 files changed, 5 insertions(+), 28 deletions(-)
diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
index 8aa0f8a..bdcf6bc 100644
--- a/hw/arm/pxa2xx.c
+++ b/hw/arm/pxa2xx.c
@@ -1449,17 +1449,10 @@ static const VMStateDescription vmstate_pxa2xx_i2c = {
}
};
-static int pxa2xx_i2c_slave_init(I2CSlave *i2c)
-{
- /* Nothing to do. */
- return 0;
-}
-
static void pxa2xx_i2c_slave_class_init(ObjectClass *klass, void *data)
{
I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
- k->init = pxa2xx_i2c_slave_init;
k->event = pxa2xx_i2c_event;
k->recv = pxa2xx_i2c_rx;
k->send = pxa2xx_i2c_tx;
diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c
index 1ee12f4..39d9dbb 100644
--- a/hw/arm/tosa.c
+++ b/hw/arm/tosa.c
@@ -202,12 +202,6 @@ static int tosa_dac_recv(I2CSlave *s)
return -1;
}
-static int tosa_dac_init(I2CSlave *i2c)
-{
- /* Nothing to do. */
- return 0;
-}
-
static void tosa_tg_init(PXA2xxState *cpu)
{
I2CBus *bus = pxa2xx_i2c_bus(cpu->i2c[0]);
@@ -275,7 +269,6 @@ static void tosa_dac_class_init(ObjectClass *klass, void *data)
{
I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
- k->init = tosa_dac_init;
k->event = tosa_dac_event;
k->recv = tosa_dac_recv;
k->send = tosa_dac_send;
diff --git a/hw/arm/z2.c b/hw/arm/z2.c
index 68a92f3..b3a6bbd 100644
--- a/hw/arm/z2.c
+++ b/hw/arm/z2.c
@@ -263,12 +263,6 @@ static int aer915_recv(I2CSlave *slave)
return retval;
}
-static int aer915_init(I2CSlave *i2c)
-{
- /* Nothing to do. */
- return 0;
-}
-
static VMStateDescription vmstate_aer915_state = {
.name = "aer915",
.version_id = 1,
@@ -285,7 +279,6 @@ static void aer915_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
- k->init = aer915_init;
k->event = aer915_event;
k->recv = aer915_recv;
k->send = aer915_send;
diff --git a/hw/i2c/core.c b/hw/i2c/core.c
index abd4c4c..ae3ca94 100644
--- a/hw/i2c/core.c
+++ b/hw/i2c/core.c
@@ -260,7 +260,11 @@ static int i2c_slave_qdev_init(DeviceState *dev)
I2CSlave *s = I2C_SLAVE(dev);
I2CSlaveClass *sc = I2C_SLAVE_GET_CLASS(s);
- return sc->init(s);
+ if (sc->init) {
+ return sc->init(s);
+ } else {
+ return 0;
+ }
}
DeviceState *i2c_create_slave(I2CBus *bus, const char *name, uint8_t addr)
diff --git a/hw/timer/ds1338.c b/hw/timer/ds1338.c
index 0112949..f5d04dd 100644
--- a/hw/timer/ds1338.c
+++ b/hw/timer/ds1338.c
@@ -198,11 +198,6 @@ static int ds1338_send(I2CSlave *i2c, uint8_t data)
return 0;
}
-static int ds1338_init(I2CSlave *i2c)
-{
- return 0;
-}
-
static void ds1338_reset(DeviceState *dev)
{
DS1338State *s = DS1338(dev);
@@ -220,7 +215,6 @@ static void ds1338_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
- k->init = ds1338_init;
k->event = ds1338_event;
k->recv = ds1338_recv;
k->send = ds1338_send;
--
2.9.3
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [Qemu-arm] [PATCH v3 3/7] hw/i2c: Add a NULL check for i2c slave init callbacks
2016-12-02 5:46 ` [Qemu-devel] [PATCH v3 3/7] hw/i2c: Add a NULL check for i2c slave init callbacks Alastair D'Silva
@ 2016-12-14 18:05 ` Peter Maydell
0 siblings, 0 replies; 16+ messages in thread
From: Peter Maydell @ 2016-12-14 18:05 UTC (permalink / raw)
To: Alastair D'Silva
Cc: Andrew Jeffery, QEMU Developers, qemu-arm, Joel Stanley,
Alastair D'Silva, Cédric Le Goater
On 2 December 2016 at 05:46, Alastair D'Silva <alastair@au1.ibm.com> wrote:
> From: Alastair D'Silva <alastair@d-silva.org>
>
> Add a NULL check for i2c slave init callbacks, so that we no longer need to implement empty init functions.
>
> Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
> ---
> hw/arm/pxa2xx.c | 7 -------
> hw/arm/tosa.c | 7 -------
> hw/arm/z2.c | 7 -------
> hw/i2c/core.c | 6 +++++-
> hw/timer/ds1338.c | 6 ------
> 5 files changed, 5 insertions(+), 28 deletions(-)
>
Applied this patch to target-arm.next for 2.9.
thanks
-- PMM
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH v3 4/7] qtest: Support named interrupts
2016-12-02 5:46 [Qemu-arm] [PATCH v3 0/7] Add support for the Epson RX8900 RTC to the aspeed board Alastair D'Silva
` (2 preceding siblings ...)
2016-12-02 5:46 ` [Qemu-devel] [PATCH v3 3/7] hw/i2c: Add a NULL check for i2c slave init callbacks Alastair D'Silva
@ 2016-12-02 5:46 ` Alastair D'Silva
2016-12-14 18:29 ` [Qemu-arm] " Peter Maydell
2016-12-02 5:46 ` [Qemu-arm] [PATCH v3 5/7] hw/timer: Add Epson RX8900 RTC support Alastair D'Silva
` (2 subsequent siblings)
6 siblings, 1 reply; 16+ messages in thread
From: Alastair D'Silva @ 2016-12-02 5:46 UTC (permalink / raw)
To: qemu-arm
Cc: Peter Maydell, Andrew Jeffery, qemu-devel, Joel Stanley,
Alastair D'Silva, Cédric Le Goater
From: Alastair D'Silva <alastair@d-silva.org>
The QTest framework cannot work with named interrupts. This patch
adds support for them, as well as the ability to manipulate them
from within a test.
Read actions are via callbacks, which allows for pulsed interrupts
to be read (the polled method used for the unnamed interrupts
cannot read pulsed interrupts as the value is reverted before the
test sees the changes).
Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
---
hw/core/irq.c | 18 +++++-----
include/hw/irq.h | 13 +++++--
qtest.c | 102 ++++++++++++++++++++++++++++++++++++++++++-------------
tests/libqtest.c | 88 ++++++++++++++++++++++++++++++++++++++++++++---
tests/libqtest.h | 59 ++++++++++++++++++++++++++++++++
5 files changed, 241 insertions(+), 39 deletions(-)
diff --git a/hw/core/irq.c b/hw/core/irq.c
index 49ff2e6..75f915b 100644
--- a/hw/core/irq.c
+++ b/hw/core/irq.c
@@ -134,15 +134,17 @@ qemu_irq *qemu_irq_proxy(qemu_irq **target, int n)
return qemu_allocate_irqs(proxy_irq_handler, target, n);
}
-void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n)
+qemu_irq qemu_irq_dup(qemu_irq in)
{
- int i;
- qemu_irq *old_irqs = qemu_allocate_irqs(NULL, NULL, n);
- for (i = 0; i < n; i++) {
- *old_irqs[i] = *gpio_in[i];
- gpio_in[i]->handler = handler;
- gpio_in[i]->opaque = &old_irqs[i];
- }
+ qemu_irq out = qemu_allocate_irq(in->handler, in->opaque, in->n);
+ return out;
+}
+
+void qemu_irq_intercept_in(qemu_irq gpio_in, qemu_irq_handler handler,
+ void *opaque)
+{
+ gpio_in->handler = handler;
+ gpio_in->opaque = opaque;
}
static const TypeInfo irq_type_info = {
diff --git a/include/hw/irq.h b/include/hw/irq.h
index 4c4c2ea..2583fd1 100644
--- a/include/hw/irq.h
+++ b/include/hw/irq.h
@@ -58,8 +58,15 @@ qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2);
*/
qemu_irq *qemu_irq_proxy(qemu_irq **target, int n);
-/* For internal use in qtest. Similar to qemu_irq_split, but operating
- on an existing vector of qemu_irq. */
-void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n);
+/**
+ * Duplicate an IRQ
+ * @param in the IRQ to deplicate
+ * @return a copy of the IRQ
+ */
+qemu_irq qemu_irq_dup(qemu_irq in);
+
+/* For internal use in qtest. */
+void qemu_irq_intercept_in(qemu_irq gpio_in, qemu_irq_handler handler,
+ void *opaque);
#endif
diff --git a/qtest.c b/qtest.c
index 46b99ae..2e09634 100644
--- a/qtest.c
+++ b/qtest.c
@@ -40,7 +40,6 @@ static DeviceState *irq_intercept_dev;
static FILE *qtest_log_fp;
static CharBackend qtest_chr;
static GString *inbuf;
-static int irq_levels[MAX_IRQ];
static qemu_timeval start_time;
static bool qtest_opened;
@@ -160,10 +159,16 @@ static bool qtest_opened;
*
* IRQ raise NUM
* IRQ lower NUM
+ * IRQ_NAMED NAME NUM LEVEL
*
* where NUM is an IRQ number. For the PC, interrupts can be intercepted
* simply with "irq_intercept_in ioapic" (note that IRQ0 comes out with
* NUM=0 even though it is remapped to GSI 2).
+ *
+ * > irq_set NAME NUM LEVEL
+ * < OK
+ *
+ * Set the named input IRQ to the level (0/1)
*/
static int hex2nib(char ch)
@@ -243,17 +248,31 @@ static void GCC_FMT_ATTR(2, 3) qtest_sendf(CharBackend *chr,
va_end(ap);
}
+typedef struct qtest_irq {
+ qemu_irq old_irq;
+ char *name;
+ bool last_level;
+} qtest_irq;
+
static void qtest_irq_handler(void *opaque, int n, int level)
{
- qemu_irq old_irq = *(qemu_irq *)opaque;
- qemu_set_irq(old_irq, level);
+ qtest_irq *data = (qtest_irq *)opaque;
+ level = !!level;
+
+ qemu_set_irq(data->old_irq, level);
- if (irq_levels[n] != level) {
+ if (level != data->last_level) {
CharBackend *chr = &qtest_chr;
- irq_levels[n] = level;
qtest_send_prefix(chr);
- qtest_sendf(chr, "IRQ %s %d\n",
- level ? "raise" : "lower", n);
+
+ if (data->name) {
+ qtest_sendf(chr, "IRQ_NAMED %s %d %d\n",
+ data->name, n, level);
+ } else {
+ qtest_sendf(chr, "IRQ %s %d\n", level ? "raise" : "lower", n);
+ }
+
+ data->last_level = level;
}
}
@@ -289,7 +308,7 @@ static void qtest_process_command(CharBackend *chr, gchar **words)
if (!dev) {
qtest_send_prefix(chr);
qtest_send(chr, "FAIL Unknown device\n");
- return;
+ return;
}
if (irq_intercept_dev) {
@@ -299,33 +318,73 @@ static void qtest_process_command(CharBackend *chr, gchar **words)
} else {
qtest_send(chr, "OK\n");
}
- return;
+ return;
}
QLIST_FOREACH(ngl, &dev->gpios, node) {
- /* We don't support intercept of named GPIOs yet */
- if (ngl->name) {
- continue;
- }
if (words[0][14] == 'o') {
int i;
for (i = 0; i < ngl->num_out; ++i) {
- qemu_irq *disconnected = g_new0(qemu_irq, 1);
- qemu_irq icpt = qemu_allocate_irq(qtest_irq_handler,
- disconnected, i);
+ qtest_irq *data = g_new0(qtest_irq, 1);
+ data->name = ngl->name;
+ qemu_irq icpt = qemu_allocate_irq(qtest_irq_handler, data,
+ i);
- *disconnected = qdev_intercept_gpio_out(dev, icpt,
+ data->old_irq = qdev_intercept_gpio_out(dev, icpt,
ngl->name, i);
}
} else {
- qemu_irq_intercept_in(ngl->in, qtest_irq_handler,
- ngl->num_in);
+ int i;
+ for (i = 0; i < ngl->num_in; ++i) {
+ qtest_irq *data = g_new0(qtest_irq, 1);
+ data->name = ngl->name;
+ data->old_irq = qemu_irq_dup(ngl->in[i]);
+
+ qemu_irq_intercept_in(ngl->in[i], qtest_irq_handler, data);
+ }
}
}
irq_intercept_dev = dev;
qtest_send_prefix(chr);
qtest_send(chr, "OK\n");
+ } else if (strcmp(words[0], "irq_set") == 0) {
+ DeviceState *dev;
+ NamedGPIOList *ngl;
+ int level;
+ qemu_irq irq = NULL;
+ int irq_num;
+
+ g_assert(words[1]); /* device */
+ g_assert(words[2]); /* gpio list */
+ g_assert(words[3]); /* gpio line in list */
+ g_assert(words[4]); /* level */
+ dev = DEVICE(object_resolve_path(words[1], NULL));
+ if (!dev) {
+ qtest_send_prefix(chr);
+ qtest_send(chr, "FAIL Unknown device\n");
+ return;
+ }
+
+ irq_num = atoi(words[3]);
+ level = atoi(words[4]);
+
+ QLIST_FOREACH(ngl, &dev->gpios, node) {
+ if (strcmp(words[2], ngl->name) == 0 && ngl->num_in > irq_num) {
+ irq = ngl->in[irq_num];
+ }
+ }
+
+ if (irq == NULL) {
+ qtest_send_prefix(chr);
+ qtest_send(chr, "FAIL Unknown IRQ\n");
+ return;
+ }
+
+ qemu_set_irq(irq, level);
+
+ qtest_send_prefix(chr);
+ qtest_send(chr, "OK\n");
} else if (strcmp(words[0], "outb") == 0 ||
strcmp(words[0], "outw") == 0 ||
strcmp(words[0], "outl") == 0) {
@@ -622,8 +681,6 @@ static int qtest_can_read(void *opaque)
static void qtest_event(void *opaque, int event)
{
- int i;
-
switch (event) {
case CHR_EVENT_OPENED:
/*
@@ -632,9 +689,6 @@ static void qtest_event(void *opaque, int event)
* used. Injects an extra reset even when it's not used, and
* that can mess up tests, e.g. -boot once.
*/
- for (i = 0; i < ARRAY_SIZE(irq_levels); i++) {
- irq_levels[i] = 0;
- }
qemu_gettimeofday(&start_time);
qtest_opened = true;
if (qtest_log_fp) {
diff --git a/tests/libqtest.c b/tests/libqtest.c
index 6f69752..36b3960 100644
--- a/tests/libqtest.c
+++ b/tests/libqtest.c
@@ -21,12 +21,16 @@
#include <sys/wait.h>
#include <sys/un.h>
+#include <glib.h>
+
#include "qapi/qmp/json-parser.h"
#include "qapi/qmp/json-streamer.h"
#include "qapi/qmp/qjson.h"
+
#define MAX_IRQ 256
#define SOCKET_TIMEOUT 50
+#define IRQ_KEY_LENGTH 64
QTestState *global_qtest;
@@ -34,12 +38,22 @@ struct QTestState
{
int fd;
int qmp_fd;
+ GHashTable *irq_handlers;
bool irq_level[MAX_IRQ];
GString *rx;
pid_t qemu_pid; /* our child QEMU process */
bool big_endian;
};
+typedef struct irq_action {
+ void (*cb)(void *opaque, const char *name, int irq, bool level);
+ void *opaque;
+ const char *name;
+ int n;
+ bool level;
+} irq_action;
+
+
static GHookList abrt_hooks;
static GList *qtest_instances;
static struct sigaction sigact_old;
@@ -216,6 +230,9 @@ QTestState *qtest_init(const char *extra_args)
s->big_endian = qtest_query_target_endianness(s);
+ s->irq_handlers = g_hash_table_new_full(g_str_hash, g_str_equal, g_free,
+ g_free);
+
return s;
}
@@ -224,6 +241,8 @@ void qtest_quit(QTestState *s)
qtest_instances = g_list_remove(qtest_instances, s);
g_hook_destroy_link(&abrt_hooks, g_hook_find_data(&abrt_hooks, TRUE, s));
+ g_hash_table_destroy(s->irq_handlers);
+
/* Uninstall SIGABRT handler on last instance */
if (!qtest_instances) {
cleanup_sigabrt_handler();
@@ -304,11 +323,35 @@ static GString *qtest_recv_line(QTestState *s)
return line;
}
+void qtest_irq_attach(QTestState *s, const char *name, int irq,
+ void (*irq_cb)(void *opaque, const char *name, int irq, bool level),
+ void *opaque)
+{
+ char key[IRQ_KEY_LENGTH];
+ irq_action *action = g_new0(irq_action, 1);
+
+ action->cb = irq_cb;
+ action->name = name;
+ action->n = irq;
+ action->opaque = opaque;
+ action->level = false;
+
+ g_assert_cmpint(snprintf(key, sizeof(key), "%s.%d",
+ name, irq), <, sizeof(key));
+
+ g_hash_table_insert(s->irq_handlers, g_strdup(key), action);
+}
+
+#define MAX_ACTIONS 256
static gchar **qtest_rsp(QTestState *s, int expected_args)
{
GString *line;
gchar **words;
int i;
+ int action_index;
+ int action_count = 0;
+ bool action_raise[MAX_ACTIONS];
+ irq_action *actions[MAX_ACTIONS];
redo:
line = qtest_recv_line(s);
@@ -325,10 +368,29 @@ redo:
g_assert_cmpint(irq, >=, 0);
g_assert_cmpint(irq, <, MAX_IRQ);
- if (strcmp(words[1], "raise") == 0) {
- s->irq_level[irq] = true;
- } else {
- s->irq_level[irq] = false;
+ s->irq_level[irq] = (strcmp(words[1], "raise") == 0);
+
+ g_strfreev(words);
+ goto redo;
+ } else if (strcmp(words[0], "IRQ_NAMED") == 0) {
+ bool level;
+ char key[IRQ_KEY_LENGTH];
+ irq_action *action;
+
+ g_assert(words[1] != NULL);
+ g_assert(words[2] != NULL);
+ g_assert(words[3] != NULL);
+
+ level = (words[3][0] == '1');
+
+ g_assert_cmpint(snprintf(key, sizeof(key), "%s.%s",
+ words[1], words[2]), <, sizeof(key));
+
+ action = g_hash_table_lookup(s->irq_handlers, key);
+
+ if (action) {
+ action_raise[action_count] = level;
+ actions[action_count++] = action;
}
g_strfreev(words);
@@ -346,6 +408,17 @@ redo:
g_strfreev(words);
}
+/* Defer processing of IRQ actions until all communications have been handled,
+ * otherwise, interrupt handler that cause further communication can disrupt
+ * the communication stream
+ */
+ for (action_index = 0; action_index < action_count; action_index++) {
+ irq_action *action = actions[action_index];
+ action->cb(action->opaque, action->name, action->n,
+ action_raise[action_index]);
+ action->level = action_raise[action_index];
+ }
+
return words;
}
@@ -918,3 +991,10 @@ bool qtest_big_endian(QTestState *s)
{
return s->big_endian;
}
+
+void qtest_irq_set(QTestState *s, const char *id, const char *gpiolist, int n,
+ bool level)
+{
+ qtest_sendf(s, "irq_set %s %s %d %d\n", id, gpiolist, n, level);
+ qtest_rsp(s, 0);
+}
diff --git a/tests/libqtest.h b/tests/libqtest.h
index 90f182e..c74373c 100644
--- a/tests/libqtest.h
+++ b/tests/libqtest.h
@@ -176,6 +176,34 @@ void qtest_irq_intercept_in(QTestState *s, const char *string);
void qtest_irq_intercept_out(QTestState *s, const char *string);
/**
+ * irq_attach:
+ * @s: #QTestState instance to operate on.
+ * @name: the name of the GPIO list containing the IRQ
+ * @irq: The IRQ number within the GPIO list to attach to
+ * @irq_cb: The callback to execute when the interrupt changes
+ * @opaque: opaque info to pass to the callback
+ *
+ * Attach a callback to an intercepted interrupt
+ */
+void qtest_irq_attach(QTestState *s, const char *name, int irq,
+ void (*irq_cb)(void *opaque, const char *name, int irq, bool level),
+ void *opaque);
+
+/**
+ * qtest_irq_set
+ * Set an interrupt level
+ * @s: #QTestState instance to operate on.
+ * @id: the device to inject interrupts for
+ * @gpiolist: the GPIO list containing the IRQ
+ * @n: the GPIO within the list
+ * @level: the IRQ level
+ *
+ * Set an interrupt to a nominated level
+ */
+void qtest_irq_set(QTestState *s, const char *id, const char *gpiolist, int n,
+ bool level);
+
+/**
* qtest_outb:
* @s: #QTestState instance to operate on.
* @addr: I/O port to write to.
@@ -626,6 +654,37 @@ static inline void irq_intercept_out(const char *string)
}
/**
+ * irq_attach:
+ * @name: the name of the gpio list containing the IRQ
+ * @irq: The IRQ to attach to
+ * @irq_cb: The callback to execute when the interrupt changes
+ * @opaque: opaque info to pass to the callback
+ *
+ * Attach a callback to an intecepted interrupt
+ */
+static inline void irq_attach(const char *name, int irq,
+ void (*irq_cb)(void *opaque, const char *name, int irq, bool level),
+ void *opaque)
+{
+ qtest_irq_attach(global_qtest, name, irq, irq_cb, opaque);
+}
+
+/**
+ * qtest_irq_set
+ * Set an interrupt level
+ * @id: the device to inject interrupts for
+ * @gpiolist: the GPIO list containing the line to seh
+ * @n: the line to set within the list
+ * @level: the IRQ level
+ */
+static inline void irq_set(const char *id, const char *gpiolist, int n,
+ bool level)
+{
+ qtest_irq_set(global_qtest, id, gpiolist, n, level);
+}
+
+
+/**
* outb:
* @addr: I/O port to write to.
* @value: Value being written.
--
2.9.3
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [Qemu-arm] [PATCH v3 4/7] qtest: Support named interrupts
2016-12-02 5:46 ` [Qemu-devel] [PATCH v3 4/7] qtest: Support named interrupts Alastair D'Silva
@ 2016-12-14 18:29 ` Peter Maydell
2016-12-14 23:19 ` Alastair D'Silva
0 siblings, 1 reply; 16+ messages in thread
From: Peter Maydell @ 2016-12-14 18:29 UTC (permalink / raw)
To: Alastair D'Silva
Cc: Andrew Jeffery, QEMU Developers, qemu-arm, Joel Stanley,
Alastair D'Silva, Cédric Le Goater
On 2 December 2016 at 05:46, Alastair D'Silva <alastair@au1.ibm.com> wrote:
> From: Alastair D'Silva <alastair@d-silva.org>
>
> The QTest framework cannot work with named interrupts. This patch
> adds support for them, as well as the ability to manipulate them
> from within a test.
>
> Read actions are via callbacks, which allows for pulsed interrupts
> to be read (the polled method used for the unnamed interrupts
> cannot read pulsed interrupts as the value is reverted before the
> test sees the changes).
>
> Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
> --- a/qtest.c
> +++ b/qtest.c
> @@ -40,7 +40,6 @@ static DeviceState *irq_intercept_dev;
> static FILE *qtest_log_fp;
> static CharBackend qtest_chr;
> static GString *inbuf;
> -static int irq_levels[MAX_IRQ];
> static qemu_timeval start_time;
> static bool qtest_opened;
>
> @@ -160,10 +159,16 @@ static bool qtest_opened;
> *
> * IRQ raise NUM
> * IRQ lower NUM
> + * IRQ_NAMED NAME NUM LEVEL
I think we should be consistent about the protocol here:
unnamed IRQs get 'raise' and 'lower' messages, so we should
do the same for named IRQs.
> *
> * where NUM is an IRQ number. For the PC, interrupts can be intercepted
> * simply with "irq_intercept_in ioapic" (note that IRQ0 comes out with
> * NUM=0 even though it is remapped to GSI 2).
> + *
> + * > irq_set NAME NUM LEVEL
> + * < OK
> + *
> + * Set the named input IRQ to the level (0/1)
I think adding support for raising and lowering device IRQs
should be a separate patch, as it's a different feature.
(I'm also not sure we should need it -- devices will be
wired into the system, and qtest is testing the whole
system from the point of view of the CPU. The CPU can't
arbitrarily reach in and assert a device's outgoing
interrupt line, so I'm not sure the tests should be able
to do it either.)
(Everything else below here is trivial fixes.)
> */
>
> static int hex2nib(char ch)
> @@ -243,17 +248,31 @@ static void GCC_FMT_ATTR(2, 3) qtest_sendf(CharBackend *chr,
> va_end(ap);
> }
>
> +typedef struct qtest_irq {
> + qemu_irq old_irq;
> + char *name;
> + bool last_level;
> +} qtest_irq;
> +
> static void qtest_irq_handler(void *opaque, int n, int level)
> {
> - qemu_irq old_irq = *(qemu_irq *)opaque;
> - qemu_set_irq(old_irq, level);
> + qtest_irq *data = (qtest_irq *)opaque;
> + level = !!level;
> +
> + qemu_set_irq(data->old_irq, level);
>
> - if (irq_levels[n] != level) {
> + if (level != data->last_level) {
> CharBackend *chr = &qtest_chr;
> - irq_levels[n] = level;
> qtest_send_prefix(chr);
> - qtest_sendf(chr, "IRQ %s %d\n",
> - level ? "raise" : "lower", n);
> +
> + if (data->name) {
> + qtest_sendf(chr, "IRQ_NAMED %s %d %d\n",
> + data->name, n, level);
> + } else {
> + qtest_sendf(chr, "IRQ %s %d\n", level ? "raise" : "lower", n);
> + }
> +
> + data->last_level = level;
> }
> }
>
> @@ -289,7 +308,7 @@ static void qtest_process_command(CharBackend *chr, gchar **words)
> if (!dev) {
> qtest_send_prefix(chr);
> qtest_send(chr, "FAIL Unknown device\n");
> - return;
> + return;
> }
>
> if (irq_intercept_dev) {
> @@ -299,33 +318,73 @@ static void qtest_process_command(CharBackend *chr, gchar **words)
> } else {
> qtest_send(chr, "OK\n");
> }
> - return;
> + return;
> }
Fixing whitespace issues is generally best done in a separate patch.
> diff --git a/tests/libqtest.c b/tests/libqtest.c
> index 6f69752..36b3960 100644
> --- a/tests/libqtest.c
> +++ b/tests/libqtest.c
> @@ -21,12 +21,16 @@
> #include <sys/wait.h>
> #include <sys/un.h>
>
> +#include <glib.h>
> +
osdep.h pulls in glib for you.
> #include "qapi/qmp/json-parser.h"
> #include "qapi/qmp/json-streamer.h"
> #include "qapi/qmp/qjson.h"
>
> +
Stray whitespace change.
> #define MAX_IRQ 256
> #define SOCKET_TIMEOUT 50
> +#define IRQ_KEY_LENGTH 64
>
> QTestState *global_qtest;
> @@ -346,6 +408,17 @@ redo:
> g_strfreev(words);
> }
>
> +/* Defer processing of IRQ actions until all communications have been handled,
> + * otherwise, interrupt handler that cause further communication can disrupt
> + * the communication stream
> + */
Bad indent on this comment.
> + for (action_index = 0; action_index < action_count; action_index++) {
> + irq_action *action = actions[action_index];
> + action->cb(action->opaque, action->name, action->n,
> + action_raise[action_index]);
> + action->level = action_raise[action_index];
> + }
> +
> return words;
> }
>
> /**
> + * irq_attach:
> + * @name: the name of the gpio list containing the IRQ
> + * @irq: The IRQ to attach to
> + * @irq_cb: The callback to execute when the interrupt changes
> + * @opaque: opaque info to pass to the callback
> + *
> + * Attach a callback to an intecepted interrupt
> + */
> +static inline void irq_attach(const char *name, int irq,
> + void (*irq_cb)(void *opaque, const char *name, int irq, bool level),
> + void *opaque)
> +{
> + qtest_irq_attach(global_qtest, name, irq, irq_cb, opaque);
> +}
> +
> +/**
> + * qtest_irq_set
Comment doesn't match function name (and missing ':').
> + * Set an interrupt level
> + * @id: the device to inject interrupts for
> + * @gpiolist: the GPIO list containing the line to seh
> + * @n: the line to set within the list
> + * @level: the IRQ level
> + */
> +static inline void irq_set(const char *id, const char *gpiolist, int n,
> + bool level)
> +{
> + qtest_irq_set(global_qtest, id, gpiolist, n, level);
> +}
> +
> +
> +/**
> * outb:
> * @addr: I/O port to write to.
> * @value: Value being written.
> --
> 2.9.3
thanks
-- PMM
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [Qemu-arm] [PATCH v3 4/7] qtest: Support named interrupts
2016-12-14 18:29 ` [Qemu-arm] " Peter Maydell
@ 2016-12-14 23:19 ` Alastair D'Silva
0 siblings, 0 replies; 16+ messages in thread
From: Alastair D'Silva @ 2016-12-14 23:19 UTC (permalink / raw)
To: Peter Maydell
Cc: Andrew Jeffery, qemu-arm, Joel Stanley, QEMU Developers,
Cédric Le Goater
On Wed, 2016-12-14 at 18:29 +0000, Peter Maydell wrote:
> On 2 December 2016 at 05:46, Alastair D'Silva <alastair@au1.ibm.com>
> wrote:
> > From: Alastair D'Silva <alastair@d-silva.org>
> >
> > The QTest framework cannot work with named interrupts. This patch
> > adds support for them, as well as the ability to manipulate them
> > from within a test.
> >
> > Read actions are via callbacks, which allows for pulsed interrupts
> > to be read (the polled method used for the unnamed interrupts
> > cannot read pulsed interrupts as the value is reverted before the
> > test sees the changes).
> >
> > Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
> > --- a/qtest.c
> > +++ b/qtest.c
> > @@ -40,7 +40,6 @@ static DeviceState *irq_intercept_dev;
> > static FILE *qtest_log_fp;
> > static CharBackend qtest_chr;
> > static GString *inbuf;
> > -static int irq_levels[MAX_IRQ];
> > static qemu_timeval start_time;
> > static bool qtest_opened;
> >
> > @@ -160,10 +159,16 @@ static bool qtest_opened;
> > *
> > * IRQ raise NUM
> > * IRQ lower NUM
> > + * IRQ_NAMED NAME NUM LEVEL
>
> I think we should be consistent about the protocol here:
> unnamed IRQs get 'raise' and 'lower' messages, so we should
> do the same for named IRQs.
>
Ok
> > *
> > * where NUM is an IRQ number. For the PC, interrupts can be
> > intercepted
> > * simply with "irq_intercept_in ioapic" (note that IRQ0 comes out
> > with
> > * NUM=0 even though it is remapped to GSI 2).
> > + *
> > + * > irq_set NAME NUM LEVEL
> > + * < OK
> > + *
> > + * Set the named input IRQ to the level (0/1)
>
> I think adding support for raising and lowering device IRQs
> should be a separate patch, as it's a different feature.
> (I'm also not sure we should need it -- devices will be
> wired into the system, and qtest is testing the whole
> system from the point of view of the CPU. The CPU can't
> arbitrarily reach in and assert a device's outgoing
> interrupt line, so I'm not sure the tests should be able
> to do it either.)
>
Unfortunately, from what I can see, the concepts of GPIO lines & IRQs
are a bit mixed up in Qemu. The use case I have is that an input line
to the chip (not an output) needs to be asserted during the test to
change it's behaviour.
> (Everything else below here is trivial fixes.)
>
> > */
> >
> > static int hex2nib(char ch)
> > @@ -243,17 +248,31 @@ static void GCC_FMT_ATTR(2, 3)
> > qtest_sendf(CharBackend *chr,
> > va_end(ap);
> > }
> >
> > +typedef struct qtest_irq {
> > + qemu_irq old_irq;
> > + char *name;
> > + bool last_level;
> > +} qtest_irq;
> > +
> > static void qtest_irq_handler(void *opaque, int n, int level)
> > {
> > - qemu_irq old_irq = *(qemu_irq *)opaque;
> > - qemu_set_irq(old_irq, level);
> > + qtest_irq *data = (qtest_irq *)opaque;
> > + level = !!level;
> > +
> > + qemu_set_irq(data->old_irq, level);
> >
> > - if (irq_levels[n] != level) {
> > + if (level != data->last_level) {
> > CharBackend *chr = &qtest_chr;
> > - irq_levels[n] = level;
> > qtest_send_prefix(chr);
> > - qtest_sendf(chr, "IRQ %s %d\n",
> > - level ? "raise" : "lower", n);
> > +
> > + if (data->name) {
> > + qtest_sendf(chr, "IRQ_NAMED %s %d %d\n",
> > + data->name, n, level);
> > + } else {
> > + qtest_sendf(chr, "IRQ %s %d\n", level ? "raise" :
> > "lower", n);
> > + }
> > +
> > + data->last_level = level;
> > }
> > }
> >
> > @@ -289,7 +308,7 @@ static void qtest_process_command(CharBackend
> > *chr, gchar **words)
> > if (!dev) {
> > qtest_send_prefix(chr);
> > qtest_send(chr, "FAIL Unknown device\n");
> > - return;
> > + return;
> > }
> >
> > if (irq_intercept_dev) {
> > @@ -299,33 +318,73 @@ static void qtest_process_command(CharBackend
> > *chr, gchar **words)
> > } else {
> > qtest_send(chr, "OK\n");
> > }
> > - return;
> > + return;
> > }
>
> Fixing whitespace issues is generally best done in a separate patch.
>
Ok
>
> > diff --git a/tests/libqtest.c b/tests/libqtest.c
> > index 6f69752..36b3960 100644
> > --- a/tests/libqtest.c
> > +++ b/tests/libqtest.c
> > @@ -21,12 +21,16 @@
> > #include <sys/wait.h>
> > #include <sys/un.h>
> >
> > +#include <glib.h>
> > +
>
> osdep.h pulls in glib for you.
>
Ok
> > #include "qapi/qmp/json-parser.h"
> > #include "qapi/qmp/json-streamer.h"
> > #include "qapi/qmp/qjson.h"
> >
> > +
>
> Stray whitespace change.
Ok
>
> > #define MAX_IRQ 256
> > #define SOCKET_TIMEOUT 50
> > +#define IRQ_KEY_LENGTH 64
> >
> > QTestState *global_qtest;
>
>
> > @@ -346,6 +408,17 @@ redo:
> > g_strfreev(words);
> > }
> >
> > +/* Defer processing of IRQ actions until all communications have
> > been handled,
> > + * otherwise, interrupt handler that cause further communication
> > can disrupt
> > + * the communication stream
> > + */
>
> Bad indent on this comment.
Ok
>
> > + for (action_index = 0; action_index < action_count;
> > action_index++) {
> > + irq_action *action = actions[action_index];
> > + action->cb(action->opaque, action->name, action->n,
> > + action_raise[action_index]);
> > + action->level = action_raise[action_index];
> > + }
> > +
> > return words;
> > }
> >
> > /**
> > + * irq_attach:
> > + * @name: the name of the gpio list containing the IRQ
> > + * @irq: The IRQ to attach to
> > + * @irq_cb: The callback to execute when the interrupt changes
> > + * @opaque: opaque info to pass to the callback
> > + *
> > + * Attach a callback to an intecepted interrupt
> > + */
> > +static inline void irq_attach(const char *name, int irq,
> > + void (*irq_cb)(void *opaque, const char *name, int irq,
> > bool level),
> > + void *opaque)
> > +{
> > + qtest_irq_attach(global_qtest, name, irq, irq_cb, opaque);
> > +}
> > +
> > +/**
> > + * qtest_irq_set
>
> Comment doesn't match function name (and missing ':').
>
Ok
> > + * Set an interrupt level
> > + * @id: the device to inject interrupts for
> > + * @gpiolist: the GPIO list containing the line to seh
> > + * @n: the line to set within the list
> > + * @level: the IRQ level
> > + */
> > +static inline void irq_set(const char *id, const char *gpiolist,
> > int n,
> > + bool level)
> > +{
> > + qtest_irq_set(global_qtest, id, gpiolist, n, level);
> > +}
> > +
> > +
> > +/**
> > * outb:
> > * @addr: I/O port to write to.
> > * @value: Value being written.
> > --
> > 2.9.3
>
> thanks
> -- PMM
>
--
Alastair D'Silva
Open Source Developer
Linux Technology Centre, IBM Australia
mob: 0423 762 819
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Qemu-arm] [PATCH v3 5/7] hw/timer: Add Epson RX8900 RTC support
2016-12-02 5:46 [Qemu-arm] [PATCH v3 0/7] Add support for the Epson RX8900 RTC to the aspeed board Alastair D'Silva
` (3 preceding siblings ...)
2016-12-02 5:46 ` [Qemu-devel] [PATCH v3 4/7] qtest: Support named interrupts Alastair D'Silva
@ 2016-12-02 5:46 ` Alastair D'Silva
2016-12-14 18:02 ` Peter Maydell
2016-12-02 5:46 ` [Qemu-arm] [PATCH v3 6/7] tests: Test all implemented RX8900 functionality Alastair D'Silva
2016-12-02 5:46 ` [Qemu-arm] [PATCH v3 7/7] arm: Add an RX8900 RTC to the ASpeed board Alastair D'Silva
6 siblings, 1 reply; 16+ messages in thread
From: Alastair D'Silva @ 2016-12-02 5:46 UTC (permalink / raw)
To: qemu-arm
Cc: Peter Maydell, Andrew Jeffery, qemu-devel, Chris Smart,
Joel Stanley, Alastair D'Silva, Cédric Le Goater
From: Alastair D'Silva <alastair@d-silva.org>
This patch adds support for the Epson RX8900 I2C RTC.
The following chip features are implemented:
- RTC (wallclock based, ptimer 10x oversampling to pick up
wallclock transitions)
- Time update interrupt (per second/minute, wallclock based)
- Alarms (wallclock based)
- Temperature (set via a property)
- Countdown timer (emulated clock via ptimer)
- FOUT via GPIO (emulated clock via ptimer)
The following chip features are unimplemented:
- Low voltage detection
- i2c timeout
The implementation exports the following named GPIOs:
rx8900-interrupt-out
rx8900-fout-enable
rx8900-fout
Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
Signed-off-by: Chris Smart <chris@distroguy.com>
---
default-configs/arm-softmmu.mak | 1 +
hw/i2c/core.c | 4 +-
hw/timer/Makefile.objs | 2 +
hw/timer/rx8900.c | 912 ++++++++++++++++++++++++++++++++++++++++
hw/timer/rx8900_regs.h | 141 +++++++
hw/timer/trace-events | 31 ++
6 files changed, 1089 insertions(+), 2 deletions(-)
create mode 100644 hw/timer/rx8900.c
create mode 100644 hw/timer/rx8900_regs.h
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 6de3e16..adb600e 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -29,6 +29,7 @@ CONFIG_SMC91C111=y
CONFIG_ALLWINNER_EMAC=y
CONFIG_IMX_FEC=y
CONFIG_DS1338=y
+CONFIG_RX8900=y
CONFIG_PFLASH_CFI01=y
CONFIG_PFLASH_CFI02=y
CONFIG_MICRODRIVE=y
diff --git a/hw/i2c/core.c b/hw/i2c/core.c
index ae3ca94..e40781e 100644
--- a/hw/i2c/core.c
+++ b/hw/i2c/core.c
@@ -262,9 +262,9 @@ static int i2c_slave_qdev_init(DeviceState *dev)
if (sc->init) {
return sc->init(s);
- } else {
- return 0;
}
+
+ return 0;
}
DeviceState *i2c_create_slave(I2CBus *bus, const char *name, uint8_t addr)
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
index 7ba8c23..fa028ac 100644
--- a/hw/timer/Makefile.objs
+++ b/hw/timer/Makefile.objs
@@ -3,6 +3,7 @@ common-obj-$(CONFIG_ARM_MPTIMER) += arm_mptimer.o
common-obj-$(CONFIG_A9_GTIMER) += a9gtimer.o
common-obj-$(CONFIG_CADENCE) += cadence_ttc.o
common-obj-$(CONFIG_DS1338) += ds1338.o
+common-obj-$(CONFIG_RX8900) += rx8900.o
common-obj-$(CONFIG_HPET) += hpet.o
common-obj-$(CONFIG_I8254) += i8254_common.o i8254.o
common-obj-$(CONFIG_M48T59) += m48t59.o
@@ -17,6 +18,7 @@ common-obj-$(CONFIG_IMX) += imx_epit.o
common-obj-$(CONFIG_IMX) += imx_gpt.o
common-obj-$(CONFIG_LM32) += lm32_timer.o
common-obj-$(CONFIG_MILKYMIST) += milkymist-sysctl.o
+common-obj-$(CONFIG_RX8900) += rx8900.o
obj-$(CONFIG_EXYNOS4) += exynos4210_mct.o
obj-$(CONFIG_EXYNOS4) += exynos4210_pwm.o
diff --git a/hw/timer/rx8900.c b/hw/timer/rx8900.c
new file mode 100644
index 0000000..6a113e4
--- /dev/null
+++ b/hw/timer/rx8900.c
@@ -0,0 +1,912 @@
+/*
+ * Epson RX8900SA/CE Realtime Clock Module
+ *
+ * Copyright (c) 2016 IBM Corporation
+ * Authors:
+ * Alastair D'Silva <alastair@d-silva.org>
+ * Chris Smart <chris@distroguy.com>
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ *
+ * Datasheet available at:
+ * https://support.epson.biz/td/api/doc_check.php?dl=app_RX8900CE&lang=en
+ *
+ * Not implemented:
+ * Implement i2c timeout
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "hw/i2c/i2c.h"
+#include "hw/timer/rx8900_regs.h"
+#include "hw/ptimer.h"
+#include "qemu/main-loop.h"
+#include "qemu/bcd.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "qapi/visitor.h"
+#include "trace.h"
+
+#define TYPE_RX8900 "rx8900"
+#define RX8900(obj) OBJECT_CHECK(RX8900State, (obj), TYPE_RX8900)
+
+typedef struct RX8900State {
+ I2CSlave parent_obj;
+
+ ptimer_state *sec_timer; /* triggered once per second */
+ ptimer_state *fout_timer;
+ ptimer_state *countdown_timer;
+ bool fout_state;
+ int64_t offset;
+ uint8_t weekday; /* Saved for deferred offset calculation, 0-6 */
+ uint8_t wday_offset;
+ uint8_t nvram[RX8900_NVRAM_SIZE];
+ int32_t nvram_offset; /* Wrapped to stay within RX8900_NVRAM_SIZE */
+ bool addr_byte;
+ uint8_t last_interrupt_seconds; /* The last time the second timer ticked */
+ /* the last minute the timer update interrupt was triggered (if enabled) */
+ uint8_t last_update_interrupt_minutes;
+ double supply_voltage;
+ qemu_irq interrupt_pin;
+ qemu_irq fout_pin;
+} RX8900State;
+
+static const VMStateDescription vmstate_rx8900 = {
+ .name = "rx8900",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_I2C_SLAVE(parent_obj, RX8900State),
+ VMSTATE_PTIMER(sec_timer, RX8900State),
+ VMSTATE_PTIMER(fout_timer, RX8900State),
+ VMSTATE_PTIMER(countdown_timer, RX8900State),
+ VMSTATE_BOOL(fout_state, RX8900State),
+ VMSTATE_INT64(offset, RX8900State),
+ VMSTATE_UINT8(weekday, RX8900State),
+ VMSTATE_UINT8(wday_offset, RX8900State),
+ VMSTATE_UINT8_ARRAY(nvram, RX8900State, RX8900_NVRAM_SIZE),
+ VMSTATE_INT32(nvram_offset, RX8900State),
+ VMSTATE_BOOL(addr_byte, RX8900State),
+ VMSTATE_UINT8(last_interrupt_seconds, RX8900State),
+ VMSTATE_UINT8(last_update_interrupt_minutes, RX8900State),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void rx8900_reset(DeviceState *dev);
+
+static void capture_current_time(RX8900State *s)
+{
+ /* Capture the current time into the secondary registers
+ * which will be actually read by the data transfer operation.
+ */
+ struct tm now;
+ qemu_get_timedate(&now, s->offset);
+ s->nvram[SECONDS] = to_bcd(now.tm_sec);
+ s->nvram[MINUTES] = to_bcd(now.tm_min);
+ s->nvram[HOURS] = to_bcd(now.tm_hour);
+
+ s->nvram[WEEKDAY] = 0x01 << ((now.tm_wday + s->wday_offset) % 7);
+ s->nvram[DAY] = to_bcd(now.tm_mday);
+ s->nvram[MONTH] = to_bcd(now.tm_mon + 1);
+ s->nvram[YEAR] = to_bcd(now.tm_year % 100);
+
+ s->nvram[EXT_SECONDS] = s->nvram[SECONDS];
+ s->nvram[EXT_MINUTES] = s->nvram[MINUTES];
+ s->nvram[EXT_HOURS] = s->nvram[HOURS];
+ s->nvram[EXT_WEEKDAY] = s->nvram[WEEKDAY];
+ s->nvram[EXT_DAY] = s->nvram[DAY];
+ s->nvram[EXT_MONTH] = s->nvram[MONTH];
+ s->nvram[EXT_YEAR] = s->nvram[YEAR];
+
+ trace_rx8900_capture_current_time(now.tm_hour, now.tm_min, now.tm_sec,
+ (now.tm_wday + s->wday_offset) % 7,
+ now.tm_mday, now.tm_mon, now.tm_year + 1900,
+ s->nvram[HOURS], s->nvram[MINUTES], s->nvram[SECONDS],
+ s->nvram[WEEKDAY], s->nvram[DAY], s->nvram[MONTH], s->nvram[YEAR]);
+}
+
+/**
+ * Increment the internal register pointer, dealing with wrapping
+ * @param s the RTC to operate on
+ */
+static void inc_regptr(RX8900State *s)
+{
+ /* The register pointer wraps around after 0x1F
+ */
+ s->nvram_offset = (s->nvram_offset + 1) & (RX8900_NVRAM_SIZE - 1);
+ trace_rx8900_regptr_update(s->nvram_offset);
+
+ if (s->nvram_offset == START_ADDRESS) {
+ trace_rx8900_regptr_overflow();
+ capture_current_time(s);
+ }
+}
+
+#define INVALID_WEEKDAY 0xff
+
+/**
+ * Receive an I2C Event
+ * @param i2c the i2c device instance
+ * @param event the event to handle
+ */
+static void rx8900_event(I2CSlave *i2c, enum i2c_event event)
+{
+ RX8900State *s = RX8900(i2c);
+
+ switch (event) {
+ case I2C_START_RECV:
+ /* In h/w, time capture happens on any START condition, not just a
+ * START_RECV. For the emulation, it doesn't actually matter,
+ * since a START_RECV has to occur before the data can be read.
+ */
+ capture_current_time(s);
+ break;
+ case I2C_START_SEND:
+ s->addr_byte = true;
+ break;
+ case I2C_FINISH:
+ if (s->weekday < 7) {
+ /* We defer the weekday calculation as it is handed to us before
+ * the date has been updated. If we calculate the weekday offset
+ * when it is passed to us, we will incorrectly determine it
+ * based on the current emulated date, rather than the date that
+ * has been written.
+ */
+ struct tm now;
+ qemu_get_timedate(&now, s->offset);
+
+ s->wday_offset = (s->weekday - now.tm_wday + 7) % 7;
+
+ trace_rx8900_event_weekday(s->weekday, BIT(s->weekday),
+ s->wday_offset);
+
+ s->weekday = INVALID_WEEKDAY;
+ }
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * Perform an i2c receive action
+ * @param i2c the i2c device instance
+ * @return the value of the current register
+ * @post the internal register pointer is incremented
+ */
+static int rx8900_recv(I2CSlave *i2c)
+{
+ RX8900State *s = RX8900(i2c);
+ uint8_t res = s->nvram[s->nvram_offset];
+ trace_rx8900_read_register(s->nvram_offset, res);
+ inc_regptr(s);
+ return res;
+}
+
+/**
+ * Disable the countdown timer
+ * @param s the RTC to operate on
+ */
+static void disable_countdown_timer(RX8900State *s)
+{
+ trace_rx8900_disable_countdown_timer();
+ ptimer_stop(s->countdown_timer);
+}
+
+/**
+ * Enable the countdown timer
+ * @param s the RTC to operate on
+ */
+static void enable_countdown_timer(RX8900State *s)
+{
+ trace_rx8900_enable_countdown_timer();
+ ptimer_run(s->countdown_timer, 0);
+}
+
+/**
+ * Tick the countdown timer
+ * @param opaque the device instance
+ */
+static void rx8900_countdown_tick(void *opaque)
+{
+ RX8900State *s = (RX8900State *)opaque;
+
+ uint16_t count = s->nvram[TIMER_COUNTER_0] |
+ ((s->nvram[TIMER_COUNTER_1] & 0x0F) << 8);
+ trace_rx8900_countdown_tick(count);
+ count--;
+
+ s->nvram[TIMER_COUNTER_0] = (uint8_t)(count & 0x00ff);
+ s->nvram[TIMER_COUNTER_1] = (uint8_t)((count & 0x0f00) >> 8);
+
+ if (count == 0) {
+ trace_rx8900_countdown_elapsed();
+
+ disable_countdown_timer(s);
+
+ s->nvram[FLAG_REGISTER] |= FLAG_MASK_TF;
+
+ if (s->nvram[CONTROL_REGISTER] & CTRL_MASK_TIE) {
+ trace_rx8900_fire_interrupt();
+ qemu_irq_pulse(s->interrupt_pin);
+ }
+ }
+}
+
+/**
+ * Disable the per second timer
+ * @param s the RTC to operate on
+ */
+static void disable_timer(RX8900State *s)
+{
+ trace_rx8900_disable_timer();
+ ptimer_stop(s->sec_timer);
+}
+
+/**
+ * Enable the per second timer
+ * @param s the RTC to operate on
+ */
+static void enable_timer(RX8900State *s)
+{
+ trace_rx8900_enable_timer();
+ ptimer_run(s->sec_timer, 0);
+}
+
+/**
+ * Tick the per second timer (can be called more frequently as it early exits
+ * if the wall clock has not progressed)
+ * @param opaque the RTC to tick
+ */
+static void rx8900_timer_tick(void *opaque)
+{
+ RX8900State *s = (RX8900State *)opaque;
+ struct tm now;
+ bool fire_interrupt = false;
+ bool alarm_week_day_matches;
+
+ qemu_get_timedate(&now, s->offset);
+
+ if (now.tm_sec == s->last_interrupt_seconds) {
+ return;
+ }
+
+ s->last_interrupt_seconds = now.tm_sec;
+
+ trace_rx8900_tick();
+
+ /* Update timer interrupt */
+ if (s->nvram[CONTROL_REGISTER] & CTRL_MASK_UIE) {
+ if ((s->nvram[EXTENSION_REGISTER] & EXT_MASK_USEL) &&
+ now.tm_min != s->last_update_interrupt_minutes) {
+ s->last_update_interrupt_minutes = now.tm_min;
+ s->nvram[FLAG_REGISTER] |= FLAG_MASK_UF;
+ fire_interrupt = true;
+ } else if (!(s->nvram[EXTENSION_REGISTER] & EXT_MASK_USEL)) {
+ /* per second update interrupt */
+ s->nvram[FLAG_REGISTER] |= FLAG_MASK_UF;
+ fire_interrupt = true;
+ }
+ }
+
+ /* Alarm interrupt */
+ if ((s->nvram[EXTENSION_REGISTER] & EXT_MASK_WADA)) {
+ alarm_week_day_matches =
+ s->nvram[ALARM_WEEK_DAY] == to_bcd(now.tm_mday);
+ } else {
+ alarm_week_day_matches =
+ s->nvram[ALARM_WEEK_DAY] ==
+ 0x01 << ((now.tm_wday + s->wday_offset) % 7);
+ }
+
+ if ((s->nvram[CONTROL_REGISTER] & CTRL_MASK_AIE) && now.tm_sec == 0 &&
+ s->nvram[ALARM_MINUTE] == to_bcd(now.tm_min) &&
+ s->nvram[ALARM_HOUR] == to_bcd(now.tm_hour) &&
+ alarm_week_day_matches) {
+ trace_rx8900_trigger_alarm();
+ s->nvram[FLAG_REGISTER] |= FLAG_MASK_AF;
+ fire_interrupt = true;
+ }
+
+ if (fire_interrupt) {
+ trace_rx8900_fire_interrupt();
+ qemu_irq_pulse(s->interrupt_pin);
+ }
+}
+
+
+#define COUNTDOWN_TIMER_FREQ 4096
+
+/**
+ * Validate the extension register and perform actions based on the bits
+ * @param s the RTC to operate on
+ * @param data the new data for the extension register
+ */
+static void update_extension_register(RX8900State *s, uint8_t data)
+{
+ if (data & EXT_MASK_TEST) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Test bit is enabled but is forbidden by the manufacturer");
+ }
+
+ if ((data ^ s->nvram[EXTENSION_REGISTER]) &
+ (EXT_MASK_FSEL0 | EXT_MASK_FSEL1)) {
+ /* FSELx has changed */
+
+ switch (data & (EXT_MASK_FSEL0 | EXT_MASK_FSEL1)) {
+ case EXT_MASK_FSEL0:
+ trace_rx8900_set_fout(1024);
+ ptimer_set_limit(s->fout_timer, 32, 1);
+ break;
+ case EXT_MASK_FSEL1:
+ trace_rx8900_set_fout(1);
+ ptimer_set_limit(s->fout_timer, 32768, 1);
+ break;
+ case 0:
+ case (EXT_MASK_FSEL0 | EXT_MASK_FSEL1):
+ trace_rx8900_set_fout(32768);
+ ptimer_set_limit(s->fout_timer, 1, 1);
+ break;
+ }
+ }
+
+ if ((data ^ s->nvram[EXTENSION_REGISTER]) &
+ (EXT_MASK_TSEL0 | EXT_MASK_TSEL1)) {
+ /* TSELx has changed */
+ switch (data & (EXT_MASK_TSEL0 | EXT_MASK_TSEL1)) {
+ case 0:
+ trace_rx8900_set_countdown_timer(64);
+ ptimer_set_limit(s->countdown_timer, COUNTDOWN_TIMER_FREQ / 64, 1);
+ break;
+ case EXT_MASK_TSEL0:
+ trace_rx8900_set_countdown_timer(1);
+ ptimer_set_limit(s->countdown_timer, COUNTDOWN_TIMER_FREQ, 1);
+ break;
+ case EXT_MASK_TSEL1:
+ trace_rx8900_set_countdown_timer_per_minute();
+ ptimer_set_limit(s->countdown_timer, COUNTDOWN_TIMER_FREQ * 60, 1);
+ break;
+ case (EXT_MASK_TSEL0 | EXT_MASK_TSEL1):
+ trace_rx8900_set_countdown_timer(COUNTDOWN_TIMER_FREQ);
+ ptimer_set_limit(s->countdown_timer, 1, 1);
+ break;
+ }
+ }
+
+ if (data & EXT_MASK_TE) {
+ enable_countdown_timer(s);
+ }
+
+ s->nvram[EXTENSION_REGISTER] = data;
+ s->nvram[EXT_EXTENSION_REGISTER] = data;
+
+}
+/**
+ * Validate the control register and perform actions based on the bits
+ * @param s the RTC to operate on
+ * @param data the new value for the control register
+ */
+
+static void update_control_register(RX8900State *s, uint8_t data)
+{
+ uint8_t diffmask = ~s->nvram[CONTROL_REGISTER] & data;
+
+ if (diffmask & CTRL_MASK_WP0) {
+ data &= ~CTRL_MASK_WP0;
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Attempt to write to write protected bit %d in control register",
+ CTRL_REG_WP0);
+ }
+
+ if (diffmask & CTRL_MASK_WP1) {
+ data &= ~CTRL_MASK_WP1;
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Attempt to write to write protected bit %d in control register",
+ CTRL_REG_WP1);
+ }
+
+ if (data & CTRL_MASK_RESET) {
+ data &= ~CTRL_MASK_RESET;
+ rx8900_reset(DEVICE(s));
+ }
+
+ if (diffmask & CTRL_MASK_UIE) {
+ /* Update interrupts were off and are now on */
+ struct tm now;
+
+ trace_rx8900_enable_update_timer();
+
+ qemu_get_timedate(&now, s->offset);
+
+ s->last_update_interrupt_minutes = now.tm_min;
+ s->last_interrupt_seconds = now.tm_sec;
+ enable_timer(s);
+ }
+
+ if (diffmask & CTRL_MASK_AIE) {
+ /* Alarm interrupts were off and are now on */
+ struct tm now;
+
+ trace_rx8900_enable_alarm();
+
+ qemu_get_timedate(&now, s->offset);
+
+ s->last_interrupt_seconds = now.tm_sec;
+ enable_timer(s);
+ }
+
+ if (!(data & (CTRL_MASK_UIE | CTRL_MASK_AIE))) {
+ disable_timer(s);
+ }
+
+ s->nvram[CONTROL_REGISTER] = data;
+ s->nvram[EXT_CONTROL_REGISTER] = data;
+}
+
+/**
+ * Validate the flag register
+ * @param s the RTC to operate on
+ * @param data the new value for the flag register
+ */
+static void validate_flag_register(RX8900State *s, uint8_t *data)
+{
+ uint8_t diffmask = ~s->nvram[FLAG_REGISTER] & *data;
+
+ if (diffmask & FLAG_MASK_VDET) {
+ *data &= ~FLAG_MASK_VDET;
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Only 0 can be written to VDET bit %d in the flag register",
+ FLAG_REG_VDET);
+ }
+
+ if (diffmask & FLAG_MASK_VLF) {
+ *data &= ~FLAG_MASK_VLF;
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Only 0 can be written to VLF bit %d in the flag register",
+ FLAG_REG_VLF);
+ }
+
+ if (diffmask & FLAG_MASK_UNUSED_2) {
+ *data &= ~FLAG_MASK_UNUSED_2;
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Only 0 can be written to unused bit %d in the flag register",
+ FLAG_REG_UNUSED_2);
+ }
+
+ if (diffmask & FLAG_MASK_UNUSED_6) {
+ *data &= ~FLAG_MASK_UNUSED_6;
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Only 0 can be written to unused bit %d in the flag register",
+ FLAG_REG_UNUSED_6);
+ }
+
+ if (diffmask & FLAG_MASK_UNUSED_7) {
+ *data &= ~FLAG_MASK_UNUSED_7;
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Only 0 can be written to unused bit %d in the flag register",
+ FLAG_REG_UNUSED_7);
+ }
+}
+
+/**
+ * Handle FOUT_ENABLE (FOE) line
+ * Enables/disables the FOUT line
+ * @param opaque the device instance
+ * @param n the IRQ number
+ * @param level true if the line has been raised
+ */
+static void rx8900_fout_enable_handler(void *opaque, int n, int level)
+{
+ RX8900State *s = RX8900(opaque);
+
+ if (level) {
+ trace_rx8900_enable_fout();
+ ptimer_run(s->fout_timer, 0);
+ } else {
+ /* disable fout */
+ trace_rx8900_disable_fout();
+ ptimer_stop(s->fout_timer);
+ }
+}
+
+/**
+ * Tick the FOUT timer
+ * @param opaque the device instance
+ */
+static void rx8900_fout_tick(void *opaque)
+{
+ RX8900State *s = (RX8900State *)opaque;
+
+ trace_rx8900_fout_toggle();
+ s->fout_state = !s->fout_state;
+
+ if (s->fout_state) {
+ qemu_irq_raise(s->fout_pin);
+ } else {
+ qemu_irq_lower(s->fout_pin);
+ }
+}
+
+/**
+ * Verify the current voltage and raise flags if it is low
+ * @param s the RTC to operate on
+ */
+static void check_voltage(RX8900State *s)
+{
+ if (!(s->nvram[BACKUP_FUNCTION] & BACKUP_MASK_VDETOFF)) {
+ if (s->supply_voltage < 2.0f) {
+ s->nvram[FLAG_REGISTER] |= FLAG_MASK_VDET;
+ }
+
+ if (s->supply_voltage < 1.6f) {
+ s->nvram[FLAG_REGISTER] |= FLAG_MASK_VLF;
+ }
+ }
+}
+
+/**
+ * Receive a byte of data from i2c
+ * @param i2c the i2c device that is receiving data
+ * @param data the data that was received
+ */
+static int rx8900_send(I2CSlave *i2c, uint8_t data)
+{
+ RX8900State *s = RX8900(i2c);
+ struct tm now;
+
+ trace_rx8900_i2c_data_receive(data);
+
+ if (s->addr_byte) {
+ s->nvram_offset = data & (RX8900_NVRAM_SIZE - 1);
+ trace_rx8900_regptr_update(s->nvram_offset);
+ s->addr_byte = false;
+ return 0;
+ }
+
+ trace_rx8900_set_register(s->nvram_offset, data);
+
+ qemu_get_timedate(&now, s->offset);
+ switch (s->nvram_offset) {
+ case SECONDS:
+ case EXT_SECONDS:
+ now.tm_sec = from_bcd(data & 0x7f);
+ if (now.tm_sec > 59) { /* RX8900 does not support leap seconds */
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "RX8900 - second data '%x' is out of range, "
+ "undefined behavior will result", data);
+ }
+ s->offset = qemu_timedate_diff(&now);
+ break;
+
+ case MINUTES:
+ case EXT_MINUTES:
+ now.tm_min = from_bcd(data & 0x7f);
+ if (now.tm_min > 59) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "RX8900 - minute data '%x' is out of range, "
+ "undefined behavior will result", data);
+ }
+ s->offset = qemu_timedate_diff(&now);
+ break;
+
+ case HOURS:
+ case EXT_HOURS:
+ now.tm_hour = from_bcd(data & 0x3f);
+ if (now.tm_hour > 24) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "RX8900 - hour data '%x' is out of range, "
+ "undefined behavior will result", data);
+ }
+ s->offset = qemu_timedate_diff(&now);
+ break;
+
+ case WEEKDAY:
+ case EXT_WEEKDAY: {
+ int user_wday = ctz32(data);
+ /* The day field is supposed to contain a value in
+ * with only 1 of bits 0-6 set. Otherwise behavior is undefined.
+ */
+ switch (data) {
+ case 0x01:
+ case 0x02:
+ case 0x04:
+ case 0x08:
+ case 0x10:
+ case 0x20:
+ case 0x40:
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "RX8900 - weekday data '%x' is out of range, "
+ "undefined behavior will result", data);
+ break;
+ }
+ s->weekday = user_wday;
+ break;
+ }
+
+ case DAY:
+ case EXT_DAY:
+ now.tm_mday = from_bcd(data & 0x3f);
+ s->offset = qemu_timedate_diff(&now);
+ break;
+
+ case MONTH:
+ case EXT_MONTH:
+ now.tm_mon = from_bcd(data & 0x1f) - 1;
+ s->offset = qemu_timedate_diff(&now);
+ break;
+
+ case YEAR:
+ case EXT_YEAR:
+ now.tm_year = from_bcd(data) + 100;
+ s->offset = qemu_timedate_diff(&now);
+ break;
+
+ case EXTENSION_REGISTER:
+ case EXT_EXTENSION_REGISTER:
+ update_extension_register(s, data);
+ break;
+
+ case FLAG_REGISTER:
+ case EXT_FLAG_REGISTER:
+ validate_flag_register(s, &data);
+
+ s->nvram[FLAG_REGISTER] = data;
+ s->nvram[EXT_FLAG_REGISTER] = data;
+
+ check_voltage(s);
+ break;
+
+ case CONTROL_REGISTER:
+ case EXT_CONTROL_REGISTER:
+ update_control_register(s, data);
+ break;
+
+ default:
+ s->nvram[s->nvram_offset] = data;
+ }
+
+ inc_regptr(s);
+ return 0;
+}
+
+/**
+ * Get the device temperature in Celcius as a property
+ * @param obj the device
+ * @param v
+ * @param name the property name
+ * @param opaque
+ * @param errp an error object to populate on failure
+ */
+static void rx8900_get_temperature(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ RX8900State *s = RX8900(obj);
+ double value = (s->nvram[TEMPERATURE] * 2.0f - 187.1f) / 3.218f;
+
+ trace_rx8900_get_temperature(s->nvram[TEMPERATURE], value);
+
+ visit_type_number(v, name, &value, errp);
+}
+
+/**
+ * Encode a temperature in Celcius
+ * @param celcius the temperature
+ * @return the encoded temperature
+ */
+static inline uint8_t encode_temperature(double celcius)
+{
+ return (uint8_t) ((celcius * 3.218f + 187.19f) / 2);
+}
+
+/**
+ * Set the device temperature in Celcius as a property
+ * @param obj the device
+ * @param v
+ * @param name the property name
+ * @param opaque
+ * @param errp an error object to populate on failure
+ */
+static void rx8900_set_temperature(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ RX8900State *s = RX8900(obj);
+ Error *local_err = NULL;
+ double temp; /* degrees Celcius */
+ visit_type_number(v, name, &temp, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+ if (temp >= 100 || temp < -58) {
+ error_setg(errp, "value %f°C is out of range", temp);
+ return;
+ }
+
+ s->nvram[TEMPERATURE] = encode_temperature(temp);
+
+ trace_rx8900_set_temperature(s->nvram[TEMPERATURE], temp);
+}
+
+/**
+ * Get the device supply voltage as a property
+ * @param obj the device
+ * @param v
+ * @param name the property name
+ * @param opaque
+ * @param errp an error object to populate on failure
+ */
+static void rx8900_get_voltage(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ RX8900State *s = RX8900(obj);
+
+ visit_type_number(v, name, &s->supply_voltage, errp);
+}
+
+/**
+ * Set the device supply voltage as a property
+ * @param obj the device
+ * @param v
+ * @param name the property name
+ * @param opaque
+ * @param errp an error object to populate on failure
+ */
+static void rx8900_set_voltage(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ RX8900State *s = RX8900(obj);
+ Error *local_err = NULL;
+ double temp;
+ visit_type_number(v, name, &temp, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
+ s->supply_voltage = temp;
+ trace_rx8900_set_voltage(s->supply_voltage);
+
+ check_voltage(s);
+}
+
+
+/**
+ * Configure device properties
+ * @param obj the device
+ */
+static void rx8900_initfn(Object *obj)
+{
+ object_property_add(obj, "temperature", "number",
+ rx8900_get_temperature,
+ rx8900_set_temperature, NULL, NULL, NULL);
+
+ object_property_add(obj, "voltage", "number",
+ rx8900_get_voltage,
+ rx8900_set_voltage, NULL, NULL, NULL);
+}
+
+/**
+ * Reset the device
+ * @param dev the RX8900 device to reset
+ */
+static void rx8900_reset(DeviceState *dev)
+{
+ RX8900State *s = RX8900(dev);
+
+ trace_rx8900_reset();
+
+ /* The clock is running and synchronized with the host */
+ s->offset = 0;
+ s->weekday = 7; /* Set to an invalid value */
+
+ s->nvram[EXTENSION_REGISTER] = EXT_MASK_TSEL1;
+ s->nvram[CONTROL_REGISTER] = CTRL_MASK_CSEL0;
+ s->nvram[FLAG_REGISTER] &= FLAG_MASK_VDET | FLAG_MASK_VLF;
+
+ s->nvram_offset = 0;
+
+ trace_rx8900_regptr_update(s->nvram_offset);
+
+ s->addr_byte = false;
+}
+
+/**
+ * Realize an RX8900 device instance
+ * Set up timers
+ * Configure GPIO lines
+ * @param dev the device instance to realize
+ * @param errp an error object to populate on error
+ */
+static void rx8900_realize(DeviceState *dev, Error **errp)
+{
+ RX8900State *s = RX8900(dev);
+ I2CSlave *i2c = I2C_SLAVE(dev);
+ QEMUBH *bh;
+ char name[64];
+
+ s->fout_state = false;
+
+ memset(s->nvram, 0, RX8900_NVRAM_SIZE);
+ /* Set the initial state to 25 degrees Celcius */
+ s->nvram[TEMPERATURE] = encode_temperature(25.0f);
+
+ /* Set up timers */
+ bh = qemu_bh_new(rx8900_timer_tick, s);
+ s->sec_timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT);
+ /* we trigger the timer at 10Hz and check for rollover, as the qemu
+ * clock does not advance in realtime in the test environment,
+ * leading to unstable test results
+ */
+ ptimer_set_freq(s->sec_timer, 10);
+ ptimer_set_limit(s->sec_timer, 1, 1);
+
+ bh = qemu_bh_new(rx8900_fout_tick, s);
+ s->fout_timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT);
+ /* frequency doubled to generate 50% duty cycle square wave */
+ ptimer_set_freq(s->fout_timer, 32768 * 2);
+ ptimer_set_limit(s->fout_timer, 1, 1);
+
+ bh = qemu_bh_new(rx8900_countdown_tick, s);
+ s->countdown_timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT);
+ ptimer_set_freq(s->countdown_timer, COUNTDOWN_TIMER_FREQ);
+ ptimer_set_limit(s->countdown_timer, COUNTDOWN_TIMER_FREQ, 1);
+
+
+ /* set up GPIO */
+ snprintf(name, sizeof(name), "rx8900-interrupt-out");
+ qdev_init_gpio_out_named(&i2c->qdev, &s->interrupt_pin, name, 1);
+ trace_rx8900_pin_name("Interrupt", name);
+
+ snprintf(name, sizeof(name), "rx8900-fout-enable");
+ qdev_init_gpio_in_named(&i2c->qdev, rx8900_fout_enable_handler, name, 1);
+ trace_rx8900_pin_name("Fout-enable", name);
+
+ snprintf(name, sizeof(name), "rx8900-fout");
+ qdev_init_gpio_out_named(&i2c->qdev, &s->fout_pin, name, 1);
+ trace_rx8900_pin_name("Fout", name);
+
+ /* Set up default voltage */
+ s->supply_voltage = 3.3f;
+ trace_rx8900_set_voltage(s->supply_voltage);
+}
+
+/**
+ * Set up the device callbacks
+ * @param klass the device class
+ * @param data
+ */
+static void rx8900_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
+
+ k->event = rx8900_event;
+ k->recv = rx8900_recv;
+ k->send = rx8900_send;
+ dc->realize = rx8900_realize;
+ dc->reset = rx8900_reset;
+ dc->vmsd = &vmstate_rx8900;
+}
+
+static const TypeInfo rx8900_info = {
+ .name = TYPE_RX8900,
+ .parent = TYPE_I2C_SLAVE,
+ .instance_size = sizeof(RX8900State),
+ .instance_init = rx8900_initfn,
+ .class_init = rx8900_class_init,
+};
+
+/**
+ * Register the device with QEMU
+ */
+static void rx8900_register_types(void)
+{
+ type_register_static(&rx8900_info);
+}
+
+type_init(rx8900_register_types)
diff --git a/hw/timer/rx8900_regs.h b/hw/timer/rx8900_regs.h
new file mode 100644
index 0000000..0aaa9a3
--- /dev/null
+++ b/hw/timer/rx8900_regs.h
@@ -0,0 +1,141 @@
+/*
+ * Epson RX8900SA/CE Realtime Clock Module
+ *
+ * Copyright (c) 2016 IBM Corporation
+ * Authors:
+ * Alastair D'Silva <alastair@d-silva.org>
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ *
+ * Datasheet available at:
+ * https://support.epson.biz/td/api/doc_check.php?dl=app_RX8900CE&lang=en
+ *
+ */
+
+#ifndef RX8900_REGS_H
+#define RX8900_REGS_H
+
+#include "qemu/bitops.h"
+
+#define RX8900_NVRAM_SIZE 0x20
+
+typedef enum RX8900Addresses {
+ START_ADDRESS = 0x00,
+ SECONDS = 0x00,
+ MINUTES = 0x01,
+ HOURS = 0x02,
+ WEEKDAY = 0x03, /* a walking bit with bit 0 set for Sunday, 1 for Monday...
+ 6 for Saturday, see the datasheet for details */
+ DAY = 0x04,
+ MONTH = 0x05,
+ YEAR = 0x06,
+ RAM = 0x07,
+ ALARM_MINUTE = 0x08,
+ ALARM_HOUR = 0x09,
+ ALARM_WEEK_DAY = 0x0A,
+ TIMER_COUNTER_0 = 0x0B,
+ TIMER_COUNTER_1 = 0x0C,
+ EXTENSION_REGISTER = 0x0D,
+ FLAG_REGISTER = 0X0E,
+ CONTROL_REGISTER = 0X0F,
+ EXT_SECONDS = 0x010, /* Alias of SECONDS */
+ EXT_MINUTES = 0x11, /* Alias of MINUTES */
+ EXT_HOURS = 0x12, /* Alias of HOURS */
+ EXT_WEEKDAY = 0x13, /* Alias of WEEKDAY */
+ EXT_DAY = 0x14, /* Alias of DAY */
+ EXT_MONTH = 0x15, /* Alias of MONTH */
+ EXT_YEAR = 0x16, /* Alias of YEAR */
+ TEMPERATURE = 0x17,
+ BACKUP_FUNCTION = 0x18,
+ NO_USE_1 = 0x19,
+ NO_USE_2 = 0x1A,
+ EXT_TIMER_COUNTER_0 = 0x1B, /* Alias of TIMER_COUNTER_0 */
+ EXT_TIMER_COUNTER_1 = 0x1C, /* Alias of TIMER_COUNTER_1 */
+ EXT_EXTENSION_REGISTER = 0x1D, /* Alias of EXTENSION_REGISTER */
+ EXT_FLAG_REGISTER = 0X1E, /* Alias of FLAG_REGISTER */
+ EXT_CONTROL_REGISTER = 0X1F /* Alias of CONTROL_REGISTER */
+} RX8900Addresses;
+
+typedef enum ExtRegBits {
+ EXT_REG_TSEL0 = 0,
+ EXT_REG_TSEL1 = 1,
+ EXT_REG_FSEL0 = 2,
+ EXT_REG_FSEL1 = 3,
+ EXT_REG_TE = 4,
+ EXT_REG_USEL = 5,
+ EXT_REG_WADA = 6,
+ EXT_REG_TEST = 7
+} ExtRegBits;
+
+typedef enum ExtRegMasks {
+ EXT_MASK_TSEL0 = BIT(0),
+ EXT_MASK_TSEL1 = BIT(1),
+ EXT_MASK_FSEL0 = BIT(2),
+ EXT_MASK_FSEL1 = BIT(3),
+ EXT_MASK_TE = BIT(4),
+ EXT_MASK_USEL = BIT(5),
+ EXT_MASK_WADA = BIT(6),
+ EXT_MASK_TEST = BIT(7)
+} ExtRegMasks;
+
+typedef enum CtrlRegBits {
+ CTRL_REG_RESET = 0,
+ CTRL_REG_WP0 = 1,
+ CTRL_REG_WP1 = 2,
+ CTRL_REG_AIE = 3,
+ CTRL_REG_TIE = 4,
+ CTRL_REG_UIE = 5,
+ CTRL_REG_CSEL0 = 6,
+ CTRL_REG_CSEL1 = 7
+} CtrlRegBits;
+
+typedef enum CtrlRegMask {
+ CTRL_MASK_RESET = BIT(0),
+ CTRL_MASK_WP0 = BIT(1),
+ CTRL_MASK_WP1 = BIT(2),
+ CTRL_MASK_AIE = BIT(3),
+ CTRL_MASK_TIE = BIT(4),
+ CTRL_MASK_UIE = BIT(5),
+ CTRL_MASK_CSEL0 = BIT(6),
+ CTRL_MASK_CSEL1 = BIT(7)
+} CtrlRegMask;
+
+typedef enum FlagRegBits {
+ FLAG_REG_VDET = 0,
+ FLAG_REG_VLF = 1,
+ FLAG_REG_UNUSED_2 = 2,
+ FLAG_REG_AF = 3,
+ FLAG_REG_TF = 4,
+ FLAG_REG_UF = 5,
+ FLAG_REG_UNUSED_6 = 6,
+ FLAG_REG_UNUSED_7 = 7
+} FlagRegBits;
+
+#define RX8900_INTERRUPT_SOURCES 6
+typedef enum FlagRegMask {
+ FLAG_MASK_VDET = BIT(0),
+ FLAG_MASK_VLF = BIT(1),
+ FLAG_MASK_UNUSED_2 = BIT(2),
+ FLAG_MASK_AF = BIT(3),
+ FLAG_MASK_TF = BIT(4),
+ FLAG_MASK_UF = BIT(5),
+ FLAG_MASK_UNUSED_6 = BIT(6),
+ FLAG_MASK_UNUSED_7 = BIT(7)
+} FlagRegMask;
+
+typedef enum BackupRegBits {
+ BACKUP_REG_BKSMP0 = 0,
+ BACKUP_REG_BKSMP1 = 1,
+ BACKUP_REG_SWOFF = 2,
+ BACKUP_REG_VDETOFF = 3
+} BackupRegBits;
+
+typedef enum BackupRegMask {
+ BACKUP_MASK_BKSMP0 = BIT(0),
+ BACKUP_MASK_BKSMP1 = BIT(1),
+ BACKUP_MASK_SWOFF = BIT(2),
+ BACKUP_MASK_VDETOFF = BIT(3)
+} BackupRegMask;
+
+#endif
diff --git a/hw/timer/trace-events b/hw/timer/trace-events
index 3495c41..7f9bb15 100644
--- a/hw/timer/trace-events
+++ b/hw/timer/trace-events
@@ -49,3 +49,34 @@ aspeed_timer_ctrl_pulse_enable(uint8_t i, bool enable) "Timer %" PRIu8 ": %d"
aspeed_timer_set_ctrl2(uint32_t value) "Value: 0x%" PRIx32
aspeed_timer_set_value(int timer, int reg, uint32_t value) "Timer %d register %d: 0x%" PRIx32
aspeed_timer_read(uint64_t offset, unsigned size, uint64_t value) "From 0x%" PRIx64 ": of size %u: 0x%" PRIx64
+
+# hw/timer/rx8900.c
+rx8900_capture_current_time(int hour, int minute, int second, int weekday, int mday, int month, int year, int raw_hours, int raw_minutes, int raw_seconds, int raw_weekday, int raw_day, int raw_month, int raw_year) "Update current time to %02d:%02d:%02d %d %d/%d/%d (0x%02x%02x%02x%02x%02x%02x%02x)"
+rx8900_regptr_update(uint32_t ptr) "Operating on register 0x%02x"
+rx8900_regptr_overflow(void) "Register pointer has overflowed, wrapping to 0"
+rx8900_event_weekday(int weekday, int weekmask, int weekday_offset) "Set weekday to %d (0x%02x), wday_offset=%d"
+rx8900_read_register(int address, int val) "Read register 0x%x = 0x%x"
+rx8900_set_fout(int hz) "Setting fout to %dHz"
+rx8900_set_countdown_timer(int hz) "Setting countdown timer to %d Hz"
+rx8900_set_countdown_timer_per_minute(void) "Setting countdown timer to per minute updates"
+rx8900_enable_update_timer(void) ""
+rx8900_enable_alarm(void) ""
+rx8900_trigger_alarm(void) ""
+rx8900_tick(void) ""
+rx8900_fire_interrupt(void) ""
+rx8900_disable_timer(void) ""
+rx8900_enable_timer(void) ""
+rx8900_disable_fout(void) ""
+rx8900_enable_fout(void) ""
+rx8900_fout_toggle(void) ""
+rx8900_disable_countdown_timer(void) ""
+rx8900_enable_countdown_timer(void) ""
+rx8900_countdown_tick(int count) "Countdown tick, count=%d"
+rx8900_countdown_elapsed(void) ""
+rx8900_i2c_data_receive(uint8_t data) "Received I2C data 0x%02x"
+rx8900_set_register(uint32_t addr, uint8_t data) "Set data 0x%02x=0x%02x"
+rx8900_get_temperature(uint8_t raw, double val) "0x%x = %f°C"
+rx8900_set_temperature(uint8_t raw, double val) "0x%x = %f°C"
+rx8900_reset(void) ""
+rx8900_pin_name(const char *type, const char *name) "'%s' pin is '%s'"
+rx8900_set_voltage(double voltage) "Device voltage set to %f"
--
2.9.3
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [Qemu-arm] [PATCH v3 5/7] hw/timer: Add Epson RX8900 RTC support
2016-12-02 5:46 ` [Qemu-arm] [PATCH v3 5/7] hw/timer: Add Epson RX8900 RTC support Alastair D'Silva
@ 2016-12-14 18:02 ` Peter Maydell
2016-12-15 0:48 ` Alastair D'Silva
0 siblings, 1 reply; 16+ messages in thread
From: Peter Maydell @ 2016-12-14 18:02 UTC (permalink / raw)
To: Alastair D'Silva
Cc: Andrew Jeffery, QEMU Developers, Chris Smart, qemu-arm,
Joel Stanley, Alastair D'Silva, Cédric Le Goater
On 2 December 2016 at 05:46, Alastair D'Silva <alastair@au1.ibm.com> wrote:
> From: Alastair D'Silva <alastair@d-silva.org>
>
> This patch adds support for the Epson RX8900 I2C RTC.
>
> The following chip features are implemented:
> - RTC (wallclock based, ptimer 10x oversampling to pick up
> wallclock transitions)
> - Time update interrupt (per second/minute, wallclock based)
> - Alarms (wallclock based)
> - Temperature (set via a property)
> - Countdown timer (emulated clock via ptimer)
> - FOUT via GPIO (emulated clock via ptimer)
>
> The following chip features are unimplemented:
> - Low voltage detection
> - i2c timeout
>
> The implementation exports the following named GPIOs:
> rx8900-interrupt-out
> rx8900-fout-enable
> rx8900-fout
>
> Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
> Signed-off-by: Chris Smart <chris@distroguy.com>
> ---
> default-configs/arm-softmmu.mak | 1 +
> hw/i2c/core.c | 4 +-
> hw/timer/Makefile.objs | 2 +
> hw/timer/rx8900.c | 912 ++++++++++++++++++++++++++++++++++++++++
> hw/timer/rx8900_regs.h | 141 +++++++
> hw/timer/trace-events | 31 ++
> 6 files changed, 1089 insertions(+), 2 deletions(-)
> create mode 100644 hw/timer/rx8900.c
> create mode 100644 hw/timer/rx8900_regs.h
>
> diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
> index 6de3e16..adb600e 100644
> --- a/default-configs/arm-softmmu.mak
> +++ b/default-configs/arm-softmmu.mak
> @@ -29,6 +29,7 @@ CONFIG_SMC91C111=y
> CONFIG_ALLWINNER_EMAC=y
> CONFIG_IMX_FEC=y
> CONFIG_DS1338=y
> +CONFIG_RX8900=y
> CONFIG_PFLASH_CFI01=y
> CONFIG_PFLASH_CFI02=y
> CONFIG_MICRODRIVE=y
> diff --git a/hw/i2c/core.c b/hw/i2c/core.c
> index ae3ca94..e40781e 100644
> --- a/hw/i2c/core.c
> +++ b/hw/i2c/core.c
> @@ -262,9 +262,9 @@ static int i2c_slave_qdev_init(DeviceState *dev)
>
> if (sc->init) {
> return sc->init(s);
> - } else {
> - return 0;
> }
> +
> + return 0;
> }
>
This change shouldn't be in this patch.
> DeviceState *i2c_create_slave(I2CBus *bus, const char *name, uint8_t addr)
> diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
> index 7ba8c23..fa028ac 100644
> --- a/hw/timer/Makefile.objs
> +++ b/hw/timer/Makefile.objs
> @@ -3,6 +3,7 @@ common-obj-$(CONFIG_ARM_MPTIMER) += arm_mptimer.o
> common-obj-$(CONFIG_A9_GTIMER) += a9gtimer.o
> common-obj-$(CONFIG_CADENCE) += cadence_ttc.o
> common-obj-$(CONFIG_DS1338) += ds1338.o
> +common-obj-$(CONFIG_RX8900) += rx8900.o
> common-obj-$(CONFIG_HPET) += hpet.o
> common-obj-$(CONFIG_I8254) += i8254_common.o i8254.o
> common-obj-$(CONFIG_M48T59) += m48t59.o
> @@ -17,6 +18,7 @@ common-obj-$(CONFIG_IMX) += imx_epit.o
> common-obj-$(CONFIG_IMX) += imx_gpt.o
> common-obj-$(CONFIG_LM32) += lm32_timer.o
> common-obj-$(CONFIG_MILKYMIST) += milkymist-sysctl.o
> +common-obj-$(CONFIG_RX8900) += rx8900.o
>
> obj-$(CONFIG_EXYNOS4) += exynos4210_mct.o
> obj-$(CONFIG_EXYNOS4) += exynos4210_pwm.o
> +/**
> + * Get the device temperature in Celcius as a property
It's spelt "Celsius" -- please fix through the whole file.
> + * @param obj the device
> + * @param v
> + * @param name the property name
> + * @param opaque
> + * @param errp an error object to populate on failure
> + */
> +static void rx8900_get_temperature(Object *obj, Visitor *v, const char *name,
> + void *opaque, Error **errp)
> +{
> + RX8900State *s = RX8900(obj);
> + double value = (s->nvram[TEMPERATURE] * 2.0f - 187.1f) / 3.218f;
Why use 'double' for the variable when you're doing all your
arithmetic at 'float' precision because of those 'f' suffixes?
Unless there's a good reason I'd suggest dropping the 'f's and
just doing all the arithmetic at double precision.
> +static void rx8900_set_temperature(Object *obj, Visitor *v, const char *name,
> + void *opaque, Error **errp)
> +{
> + RX8900State *s = RX8900(obj);
> + Error *local_err = NULL;
> + double temp; /* degrees Celcius */
> + visit_type_number(v, name, &temp, &local_err);
> + if (local_err) {
> + error_propagate(errp, local_err);
> + return;
> + }
> + if (temp >= 100 || temp < -58) {
> + error_setg(errp, "value %f°C is out of range", temp);
Not sure that UTF-8 characters directly in error strings
is a great idea. I'd stick to ASCII.
> + return;
> + }
> +
> + s->nvram[TEMPERATURE] = encode_temperature(temp);
> +
> + trace_rx8900_set_temperature(s->nvram[TEMPERATURE], temp);
> +}
> +
> +/**
> + * Get the device supply voltage as a property
> + * @param obj the device
> + * @param v
> + * @param name the property name
> + * @param opaque
> + * @param errp an error object to populate on failure
> + */
> +static void rx8900_get_voltage(Object *obj, Visitor *v, const char *name,
> + void *opaque, Error **errp)
> +{
> + RX8900State *s = RX8900(obj);
> +
> + visit_type_number(v, name, &s->supply_voltage, errp);
> +}
> +
> +/**
> + * Set the device supply voltage as a property
> + * @param obj the device
> + * @param v
> + * @param name the property name
> + * @param opaque
> + * @param errp an error object to populate on failure
> + */
> +static void rx8900_set_voltage(Object *obj, Visitor *v, const char *name,
> + void *opaque, Error **errp)
> +{
> + RX8900State *s = RX8900(obj);
> + Error *local_err = NULL;
> + double temp;
> + visit_type_number(v, name, &temp, &local_err);
> + if (local_err) {
> + error_propagate(errp, local_err);
> + return;
> + }
> +
> + s->supply_voltage = temp;
> + trace_rx8900_set_voltage(s->supply_voltage);
> +
> + check_voltage(s);
> +}
> +
> +
> +/**
> + * Configure device properties
> + * @param obj the device
> + */
> +static void rx8900_initfn(Object *obj)
> +{
> + object_property_add(obj, "temperature", "number",
> + rx8900_get_temperature,
> + rx8900_set_temperature, NULL, NULL, NULL);
> +
> + object_property_add(obj, "voltage", "number",
> + rx8900_get_voltage,
> + rx8900_set_voltage, NULL, NULL, NULL);
> +}
> +
> +/**
> + * Reset the device
> + * @param dev the RX8900 device to reset
> + */
> +static void rx8900_reset(DeviceState *dev)
> +{
> + RX8900State *s = RX8900(dev);
> +
> + trace_rx8900_reset();
> +
> + /* The clock is running and synchronized with the host */
> + s->offset = 0;
> + s->weekday = 7; /* Set to an invalid value */
> +
> + s->nvram[EXTENSION_REGISTER] = EXT_MASK_TSEL1;
> + s->nvram[CONTROL_REGISTER] = CTRL_MASK_CSEL0;
> + s->nvram[FLAG_REGISTER] &= FLAG_MASK_VDET | FLAG_MASK_VLF;
> +
> + s->nvram_offset = 0;
> +
> + trace_rx8900_regptr_update(s->nvram_offset);
> +
> + s->addr_byte = false;
> +}
> +
> +/**
> + * Realize an RX8900 device instance
> + * Set up timers
> + * Configure GPIO lines
> + * @param dev the device instance to realize
> + * @param errp an error object to populate on error
> + */
> +static void rx8900_realize(DeviceState *dev, Error **errp)
> +{
> + RX8900State *s = RX8900(dev);
> + I2CSlave *i2c = I2C_SLAVE(dev);
> + QEMUBH *bh;
> + char name[64];
> +
> + s->fout_state = false;
> +
> + memset(s->nvram, 0, RX8900_NVRAM_SIZE);
This looks like something you should be doing in reset.
> + /* Set the initial state to 25 degrees Celcius */
> + s->nvram[TEMPERATURE] = encode_temperature(25.0f);
...and this.
> +
> + /* Set up timers */
> + bh = qemu_bh_new(rx8900_timer_tick, s);
> + s->sec_timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT);
> + /* we trigger the timer at 10Hz and check for rollover, as the qemu
> + * clock does not advance in realtime in the test environment,
> + * leading to unstable test results
> + */
> + ptimer_set_freq(s->sec_timer, 10);
> + ptimer_set_limit(s->sec_timer, 1, 1);
> +
> + bh = qemu_bh_new(rx8900_fout_tick, s);
> + s->fout_timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT);
> + /* frequency doubled to generate 50% duty cycle square wave */
> + ptimer_set_freq(s->fout_timer, 32768 * 2);
> + ptimer_set_limit(s->fout_timer, 1, 1);
> +
> + bh = qemu_bh_new(rx8900_countdown_tick, s);
> + s->countdown_timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT);
> + ptimer_set_freq(s->countdown_timer, COUNTDOWN_TIMER_FREQ);
> + ptimer_set_limit(s->countdown_timer, COUNTDOWN_TIMER_FREQ, 1);
> +
> +
> + /* set up GPIO */
> + snprintf(name, sizeof(name), "rx8900-interrupt-out");
> + qdev_init_gpio_out_named(&i2c->qdev, &s->interrupt_pin, name, 1);
> + trace_rx8900_pin_name("Interrupt", name);
> +
> + snprintf(name, sizeof(name), "rx8900-fout-enable");
> + qdev_init_gpio_in_named(&i2c->qdev, rx8900_fout_enable_handler, name, 1);
> + trace_rx8900_pin_name("Fout-enable", name);
> +
> + snprintf(name, sizeof(name), "rx8900-fout");
> + qdev_init_gpio_out_named(&i2c->qdev, &s->fout_pin, name, 1);
> + trace_rx8900_pin_name("Fout", name);
> +
> + /* Set up default voltage */
> + s->supply_voltage = 3.3f;
> + trace_rx8900_set_voltage(s->supply_voltage);
> +}
> +rx8900_get_temperature(uint8_t raw, double val) "0x%x = %f°C"
> +rx8900_set_temperature(uint8_t raw, double val) "0x%x = %f°C"
Stick to ASCII here too.
thanks
-- PMM
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [Qemu-arm] [PATCH v3 5/7] hw/timer: Add Epson RX8900 RTC support
2016-12-14 18:02 ` Peter Maydell
@ 2016-12-15 0:48 ` Alastair D'Silva
0 siblings, 0 replies; 16+ messages in thread
From: Alastair D'Silva @ 2016-12-15 0:48 UTC (permalink / raw)
To: Peter Maydell
Cc: Andrew Jeffery, QEMU Developers, Chris Smart, qemu-arm,
Joel Stanley, Cédric Le Goater
On Wed, 2016-12-14 at 18:02 +0000, Peter Maydell wrote:
> On 2 December 2016 at 05:46, Alastair D'Silva <alastair@au1.ibm.com>
> wrote:
> > From: Alastair D'Silva <alastair@d-silva.org>
> >
> > This patch adds support for the Epson RX8900 I2C RTC.
> >
> > The following chip features are implemented:
> > - RTC (wallclock based, ptimer 10x oversampling to pick up
> > wallclock transitions)
> > - Time update interrupt (per second/minute, wallclock based)
> > - Alarms (wallclock based)
> > - Temperature (set via a property)
> > - Countdown timer (emulated clock via ptimer)
> > - FOUT via GPIO (emulated clock via ptimer)
> >
> > The following chip features are unimplemented:
> > - Low voltage detection
> > - i2c timeout
> >
> > The implementation exports the following named GPIOs:
> > rx8900-interrupt-out
> > rx8900-fout-enable
> > rx8900-fout
> >
> > Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
> > Signed-off-by: Chris Smart <chris@distroguy.com>
> > ---
> > default-configs/arm-softmmu.mak | 1 +
> > hw/i2c/core.c | 4 +-
> > hw/timer/Makefile.objs | 2 +
> > hw/timer/rx8900.c | 912
> > ++++++++++++++++++++++++++++++++++++++++
> > hw/timer/rx8900_regs.h | 141 +++++++
> > hw/timer/trace-events | 31 ++
> > 6 files changed, 1089 insertions(+), 2 deletions(-)
> > create mode 100644 hw/timer/rx8900.c
> > create mode 100644 hw/timer/rx8900_regs.h
> >
> > diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-
> > softmmu.mak
> > index 6de3e16..adb600e 100644
> > --- a/default-configs/arm-softmmu.mak
> > +++ b/default-configs/arm-softmmu.mak
> > @@ -29,6 +29,7 @@ CONFIG_SMC91C111=y
> > CONFIG_ALLWINNER_EMAC=y
> > CONFIG_IMX_FEC=y
> > CONFIG_DS1338=y
> > +CONFIG_RX8900=y
> > CONFIG_PFLASH_CFI01=y
> > CONFIG_PFLASH_CFI02=y
> > CONFIG_MICRODRIVE=y
> > diff --git a/hw/i2c/core.c b/hw/i2c/core.c
> > index ae3ca94..e40781e 100644
> > --- a/hw/i2c/core.c
> > +++ b/hw/i2c/core.c
> > @@ -262,9 +262,9 @@ static int i2c_slave_qdev_init(DeviceState
> > *dev)
> >
> > if (sc->init) {
> > return sc->init(s);
> > - } else {
> > - return 0;
> > }
> > +
> > + return 0;
> > }
> >
>
> This change shouldn't be in this patch.
Ok
>
> > DeviceState *i2c_create_slave(I2CBus *bus, const char *name,
> > uint8_t addr)
> > diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
> > index 7ba8c23..fa028ac 100644
> > --- a/hw/timer/Makefile.objs
> > +++ b/hw/timer/Makefile.objs
> > @@ -3,6 +3,7 @@ common-obj-$(CONFIG_ARM_MPTIMER) += arm_mptimer.o
> > common-obj-$(CONFIG_A9_GTIMER) += a9gtimer.o
> > common-obj-$(CONFIG_CADENCE) += cadence_ttc.o
> > common-obj-$(CONFIG_DS1338) += ds1338.o
> > +common-obj-$(CONFIG_RX8900) += rx8900.o
> > common-obj-$(CONFIG_HPET) += hpet.o
> > common-obj-$(CONFIG_I8254) += i8254_common.o i8254.o
> > common-obj-$(CONFIG_M48T59) += m48t59.o
> > @@ -17,6 +18,7 @@ common-obj-$(CONFIG_IMX) += imx_epit.o
> > common-obj-$(CONFIG_IMX) += imx_gpt.o
> > common-obj-$(CONFIG_LM32) += lm32_timer.o
> > common-obj-$(CONFIG_MILKYMIST) += milkymist-sysctl.o
> > +common-obj-$(CONFIG_RX8900) += rx8900.o
> >
> > obj-$(CONFIG_EXYNOS4) += exynos4210_mct.o
> > obj-$(CONFIG_EXYNOS4) += exynos4210_pwm.o
> > +/**
> > + * Get the device temperature in Celcius as a property
>
> It's spelt "Celsius" -- please fix through the whole file.
>
Whoops, thanks for that :)
> > + * @param obj the device
> > + * @param v
> > + * @param name the property name
> > + * @param opaque
> > + * @param errp an error object to populate on failure
> > + */
> > +static void rx8900_get_temperature(Object *obj, Visitor *v, const
> > char *name,
> > + void *opaque, Error **errp)
> > +{
> > + RX8900State *s = RX8900(obj);
> > + double value = (s->nvram[TEMPERATURE] * 2.0f - 187.1f) /
> > 3.218f;
>
> Why use 'double' for the variable when you're doing all your
> arithmetic at 'float' precision because of those 'f' suffixes?
> Unless there's a good reason I'd suggest dropping the 'f's and
> just doing all the arithmetic at double precision.
Ok
> > +static void rx8900_set_temperature(Object *obj, Visitor *v, const
> > char *name,
> > + void *opaque, Error **errp)
> > +{
> > + RX8900State *s = RX8900(obj);
> > + Error *local_err = NULL;
> > + double temp; /* degrees Celcius */
> > + visit_type_number(v, name, &temp, &local_err);
> > + if (local_err) {
> > + error_propagate(errp, local_err);
> > + return;
> > + }
> > + if (temp >= 100 || temp < -58) {
> > + error_setg(errp, "value %f°C is out of range", temp);
>
> Not sure that UTF-8 characters directly in error strings
> is a great idea. I'd stick to ASCII.
It is valid 8 bit ASCII, but is code-page dependent, Ok, I'll remove
it.
> > + return;
> > + }
> > +
> > + s->nvram[TEMPERATURE] = encode_temperature(temp);
> > +
> > + trace_rx8900_set_temperature(s->nvram[TEMPERATURE], temp);
> > +}
> > +
> > +/**
> > + * Get the device supply voltage as a property
> > + * @param obj the device
> > + * @param v
> > + * @param name the property name
> > + * @param opaque
> > + * @param errp an error object to populate on failure
> > + */
> > +static void rx8900_get_voltage(Object *obj, Visitor *v, const char
> > *name,
> > + void *opaque, Error **errp)
> > +{
> > + RX8900State *s = RX8900(obj);
> > +
> > + visit_type_number(v, name, &s->supply_voltage, errp);
> > +}
> > +
> > +/**
> > + * Set the device supply voltage as a property
> > + * @param obj the device
> > + * @param v
> > + * @param name the property name
> > + * @param opaque
> > + * @param errp an error object to populate on failure
> > + */
> > +static void rx8900_set_voltage(Object *obj, Visitor *v, const char
> > *name,
> > + void *opaque, Error **errp)
> > +{
> > + RX8900State *s = RX8900(obj);
> > + Error *local_err = NULL;
> > + double temp;
> > + visit_type_number(v, name, &temp, &local_err);
> > + if (local_err) {
> > + error_propagate(errp, local_err);
> > + return;
> > + }
> > +
> > + s->supply_voltage = temp;
> > + trace_rx8900_set_voltage(s->supply_voltage);
> > +
> > + check_voltage(s);
> > +}
> > +
> > +
> > +/**
> > + * Configure device properties
> > + * @param obj the device
> > + */
> > +static void rx8900_initfn(Object *obj)
> > +{
> > + object_property_add(obj, "temperature", "number",
> > + rx8900_get_temperature,
> > + rx8900_set_temperature, NULL, NULL, NULL);
> > +
> > + object_property_add(obj, "voltage", "number",
> > + rx8900_get_voltage,
> > + rx8900_set_voltage, NULL, NULL, NULL);
> > +}
> > +
> > +/**
> > + * Reset the device
> > + * @param dev the RX8900 device to reset
> > + */
> > +static void rx8900_reset(DeviceState *dev)
> > +{
> > + RX8900State *s = RX8900(dev);
> > +
> > + trace_rx8900_reset();
> > +
> > + /* The clock is running and synchronized with the host */
> > + s->offset = 0;
> > + s->weekday = 7; /* Set to an invalid value */
> > +
> > + s->nvram[EXTENSION_REGISTER] = EXT_MASK_TSEL1;
> > + s->nvram[CONTROL_REGISTER] = CTRL_MASK_CSEL0;
> > + s->nvram[FLAG_REGISTER] &= FLAG_MASK_VDET | FLAG_MASK_VLF;
> > +
> > + s->nvram_offset = 0;
> > +
> > + trace_rx8900_regptr_update(s->nvram_offset);
> > +
> > + s->addr_byte = false;
> > +}
> > +
> > +/**
> > + * Realize an RX8900 device instance
> > + * Set up timers
> > + * Configure GPIO lines
> > + * @param dev the device instance to realize
> > + * @param errp an error object to populate on error
> > + */
> > +static void rx8900_realize(DeviceState *dev, Error **errp)
> > +{
> > + RX8900State *s = RX8900(dev);
> > + I2CSlave *i2c = I2C_SLAVE(dev);
> > + QEMUBH *bh;
> > + char name[64];
> > +
> > + s->fout_state = false;
> > +
> > + memset(s->nvram, 0, RX8900_NVRAM_SIZE);
>
> This looks like something you should be doing in reset.
>
> > + /* Set the initial state to 25 degrees Celcius */
> > + s->nvram[TEMPERATURE] = encode_temperature(25.0f);
>
> ...and this.
>
I reuse the reset code for the soft-reset, which prevents me from doing
these operations there.
> > +
> > + /* Set up timers */
> > + bh = qemu_bh_new(rx8900_timer_tick, s);
> > + s->sec_timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT);
> > + /* we trigger the timer at 10Hz and check for rollover, as the
> > qemu
> > + * clock does not advance in realtime in the test environment,
> > + * leading to unstable test results
> > + */
> > + ptimer_set_freq(s->sec_timer, 10);
> > + ptimer_set_limit(s->sec_timer, 1, 1);
> > +
> > + bh = qemu_bh_new(rx8900_fout_tick, s);
> > + s->fout_timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT);
> > + /* frequency doubled to generate 50% duty cycle square wave */
> > + ptimer_set_freq(s->fout_timer, 32768 * 2);
> > + ptimer_set_limit(s->fout_timer, 1, 1);
> > +
> > + bh = qemu_bh_new(rx8900_countdown_tick, s);
> > + s->countdown_timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT);
> > + ptimer_set_freq(s->countdown_timer, COUNTDOWN_TIMER_FREQ);
> > + ptimer_set_limit(s->countdown_timer, COUNTDOWN_TIMER_FREQ, 1);
> > +
> > +
> > + /* set up GPIO */
> > + snprintf(name, sizeof(name), "rx8900-interrupt-out");
> > + qdev_init_gpio_out_named(&i2c->qdev, &s->interrupt_pin, name,
> > 1);
> > + trace_rx8900_pin_name("Interrupt", name);
> > +
> > + snprintf(name, sizeof(name), "rx8900-fout-enable");
> > + qdev_init_gpio_in_named(&i2c->qdev,
> > rx8900_fout_enable_handler, name, 1);
> > + trace_rx8900_pin_name("Fout-enable", name);
> > +
> > + snprintf(name, sizeof(name), "rx8900-fout");
> > + qdev_init_gpio_out_named(&i2c->qdev, &s->fout_pin, name, 1);
> > + trace_rx8900_pin_name("Fout", name);
> > +
> > + /* Set up default voltage */
> > + s->supply_voltage = 3.3f;
> > + trace_rx8900_set_voltage(s->supply_voltage);
> > +}
> > +rx8900_get_temperature(uint8_t raw, double val) "0x%x = %f°C"
> > +rx8900_set_temperature(uint8_t raw, double val) "0x%x = %f°C"
>
> Stick to ASCII here too.
>
Ok
> thanks
> -- PMM
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Qemu-arm] [PATCH v3 6/7] tests: Test all implemented RX8900 functionality
2016-12-02 5:46 [Qemu-arm] [PATCH v3 0/7] Add support for the Epson RX8900 RTC to the aspeed board Alastair D'Silva
` (4 preceding siblings ...)
2016-12-02 5:46 ` [Qemu-arm] [PATCH v3 5/7] hw/timer: Add Epson RX8900 RTC support Alastair D'Silva
@ 2016-12-02 5:46 ` Alastair D'Silva
2016-12-02 5:46 ` [Qemu-arm] [PATCH v3 7/7] arm: Add an RX8900 RTC to the ASpeed board Alastair D'Silva
6 siblings, 0 replies; 16+ messages in thread
From: Alastair D'Silva @ 2016-12-02 5:46 UTC (permalink / raw)
To: qemu-arm
Cc: Peter Maydell, Andrew Jeffery, qemu-devel, Joel Stanley,
Alastair D'Silva, Cédric Le Goater
From: Alastair D'Silva <alastair@d-silva.org>
Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
---
tests/Makefile.include | 2 +
tests/rx8900-test.c | 882 +++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 884 insertions(+)
create mode 100644 tests/rx8900-test.c
diff --git a/tests/Makefile.include b/tests/Makefile.include
index e98d3b6..e52e355 100644
--- a/tests/Makefile.include
+++ b/tests/Makefile.include
@@ -300,6 +300,7 @@ check-qtest-sparc64-y = tests/endianness-test$(EXESUF)
check-qtest-arm-y = tests/tmp105-test$(EXESUF)
check-qtest-arm-y += tests/ds1338-test$(EXESUF)
+check-qtest-arm-y += tests/rx8900-test$(EXESUF)
check-qtest-arm-y += tests/m25p80-test$(EXESUF)
gcov-files-arm-y += hw/misc/tmp105.c
check-qtest-arm-y += tests/virtio-blk-test$(EXESUF)
@@ -637,6 +638,7 @@ tests/bios-tables-test$(EXESUF): tests/bios-tables-test.o \
tests/pxe-test$(EXESUF): tests/pxe-test.o tests/boot-sector.o $(libqos-obj-y)
tests/tmp105-test$(EXESUF): tests/tmp105-test.o $(libqos-omap-obj-y)
tests/ds1338-test$(EXESUF): tests/ds1338-test.o $(libqos-imx-obj-y)
+tests/rx8900-test$(EXESUF): tests/rx8900-test.o $(libqos-imx-obj-y)
tests/m25p80-test$(EXESUF): tests/m25p80-test.o
tests/i440fx-test$(EXESUF): tests/i440fx-test.o $(libqos-pc-obj-y)
tests/q35-test$(EXESUF): tests/q35-test.o $(libqos-pc-obj-y)
diff --git a/tests/rx8900-test.c b/tests/rx8900-test.c
new file mode 100644
index 0000000..1769659
--- /dev/null
+++ b/tests/rx8900-test.c
@@ -0,0 +1,882 @@
+/*
+ * QTest testcase for the Epson RX8900SA/CE RTC
+ *
+ * Copyright (c) 2016 IBM Corporation
+ * Authors:
+ * Alastair D'Silva <alastair@d-silva.org>
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/timer/rx8900_regs.h"
+#include "libqtest.h"
+#include "libqos/i2c.h"
+#include "qemu/timer.h"
+
+#define IMX25_I2C_0_BASE 0x43F80000
+#define RX8900_TEST_ID "rx8900-test"
+#define RX8900_ADDR 0x32
+#define RX8900_INTERRUPT_OUT "rx8900-interrupt-out"
+#define RX8900_FOUT_ENABLE "rx8900-fout-enable"
+#define RX8900_FOUT "rx8900-fout"
+
+static I2CAdapter *i2c;
+static uint8_t addr;
+
+static inline uint8_t bcd2bin(uint8_t x)
+{
+ return (x & 0x0f) + (x >> 4) * 10;
+}
+
+static inline uint8_t bin2bcd(uint8_t x)
+{
+ return (x / 10 << 4) | (x % 10);
+}
+
+static void qmp_rx8900_set_temperature(const char *id, double value)
+{
+ QDict *response;
+
+ response = qmp("{ 'execute': 'qom-set', 'arguments': { 'path': %s, "
+ "'property': 'temperature', 'value': %f } }", id, value);
+ g_assert(qdict_haskey(response, "return"));
+ QDECREF(response);
+}
+
+static void qmp_rx8900_set_voltage(const char *id, double value)
+{
+ QDict *response;
+
+ response = qmp("{ 'execute': 'qom-set', 'arguments': { 'path': %s, "
+ "'property': 'voltage', 'value': %f } }", id, value);
+ g_assert(qdict_haskey(response, "return"));
+ QDECREF(response);
+}
+
+/**
+ * Read an RX8900 register
+ * @param reg the address of the register
+ * @return the value of the register
+ */
+static uint8_t read_register(RX8900Addresses reg)
+{
+ uint8_t val;
+ uint8_t reg_address = (uint8_t)reg;
+
+ i2c_send(i2c, addr, ®_address, 1);
+ i2c_recv(i2c, addr, &val, 1);
+
+ return val;
+}
+
+/**
+ * Write to an RX8900 register
+ * @param reg the address of the register
+ * @param val the value to write
+ */
+static uint8_t write_register(RX8900Addresses reg, uint8_t val)
+{
+ uint8_t buf[2];
+
+ buf[0] = reg;
+ buf[1] = val;
+
+ i2c_send(i2c, addr, buf, 2);
+
+ return val;
+}
+
+/**
+ * Set bits in a register
+ * @param reg the address of the register
+ * @param mask a mask of the bits to set
+ */
+static void set_bits_in_register(RX8900Addresses reg, uint8_t mask)
+{
+ uint8_t value = read_register(reg);
+ value |= mask;
+ write_register(reg, value);
+}
+
+/**
+ * Clear bits in a register
+ * @param reg the address of the register
+ * @param mask a mask of the bits to set
+ */
+static void clear_bits_in_register(RX8900Addresses reg, uint8_t mask)
+{
+ uint8_t value = read_register(reg);
+ value &= ~mask;
+ write_register(reg, value);
+}
+
+/**
+ * Read a number of sequential RX8900 registers
+ * @param reg the address of the first register
+ * @param buf (out) an output buffer to stash the register values
+ * @param count the number of registers to read
+ */
+static void read_registers(RX8900Addresses reg, uint8_t *buf, uint8_t count)
+{
+ uint8_t reg_address = (uint8_t)reg;
+
+ i2c_send(i2c, addr, ®_address, 1);
+ i2c_recv(i2c, addr, buf, count);
+}
+
+/**
+ * Write to a sequential number of RX8900 registers
+ * @param reg the address of the first register
+ * @param buffer a buffer of values to write
+ * @param count the sumber of registers to write
+ */
+static void write_registers(RX8900Addresses reg, uint8_t *buffer, uint8_t count)
+{
+ uint8_t buf[RX8900_NVRAM_SIZE + 1];
+
+ buf[0] = (uint8_t)reg;
+ memcpy(buf + 1, buffer, count);
+
+ i2c_send(i2c, addr, buf, count + 1);
+}
+
+/**
+ * Set the time on the RX8900
+ * @param secs the seconds to set
+ * @param mins the minutes to set
+ * @param hours the hours to set
+ * @param weekday the day of the week to set (0 = Sunday)
+ * @param day the day of the month to set
+ * @param month the month to set
+ * @param year the year to set
+ */
+static void set_time(uint8_t secs, uint8_t mins, uint8_t hours,
+ uint8_t weekday, uint8_t day, uint8_t month, uint8_t year)
+{
+ uint8_t buf[7];
+
+ buf[0] = bin2bcd(secs);
+ buf[1] = bin2bcd(mins);
+ buf[2] = bin2bcd(hours);
+ buf[3] = BIT(weekday);
+ buf[4] = bin2bcd(day);
+ buf[5] = bin2bcd(month);
+ buf[6] = bin2bcd(year);
+
+ write_registers(SECONDS, buf, 7);
+}
+
+
+/**
+ * Check basic communication
+ */
+static void send_and_receive(void)
+{
+ uint8_t buf[7];
+ time_t now = time(NULL);
+ struct tm *tm_ptr;
+
+ /* retrieve the date */
+ read_registers(SECONDS, buf, 7);
+
+ tm_ptr = gmtime(&now);
+
+ /* check retrieved time against local time */
+ g_assert_cmpuint(bcd2bin(buf[0]), == , tm_ptr->tm_sec);
+ g_assert_cmpuint(bcd2bin(buf[1]), == , tm_ptr->tm_min);
+ g_assert_cmpuint(bcd2bin(buf[2]), == , tm_ptr->tm_hour);
+ g_assert_cmpuint(bcd2bin(buf[4]), == , tm_ptr->tm_mday);
+ g_assert_cmpuint(bcd2bin(buf[5]), == , 1 + tm_ptr->tm_mon);
+ g_assert_cmpuint(2000 + bcd2bin(buf[6]), == , 1900 + tm_ptr->tm_year);
+}
+
+/**
+ * Check that the temperature can be altered via properties
+ */
+static void check_temperature(void)
+{
+ /* Check the initial temperature is 25C */
+ uint8_t temperature;
+
+ temperature = read_register(TEMPERATURE);
+ g_assert_cmpuint(temperature, == , 133);
+
+ /* Set the temperature to 40C and check the temperature again */
+ qmp_rx8900_set_temperature(RX8900_TEST_ID, 40.0f);
+ temperature = read_register(TEMPERATURE);
+ g_assert_cmpuint(temperature, == , 157);
+}
+
+/**
+ * Check that the time rolls over correctly
+ */
+static void check_rollover(void)
+{
+ uint8_t buf[7];
+
+
+ set_time(59, 59, 23, 1, 29, 2, 16);
+
+ /* Wait for the clock to rollover */
+ sleep(2);
+
+ memset(buf, 0, sizeof(buf));
+
+ /* Check that the clock rolled over */
+ /* Read from registers starting at 0x00 */
+ buf[0] = 0x00;
+
+ read_registers(SECONDS, buf, 7);
+
+ /* Ignore seconds as there may be some noise,
+ * we expect 00:00:xx Tuesday 1/3/2016
+ */
+ g_assert_cmpuint(bcd2bin(buf[1]), == , 0);
+ g_assert_cmpuint(bcd2bin(buf[2]), == , 0);
+ g_assert_cmpuint(bcd2bin(buf[3]), == , 0x04);
+ g_assert_cmpuint(bcd2bin(buf[4]), == , 1);
+ g_assert_cmpuint(bcd2bin(buf[5]), == , 3);
+ g_assert_cmpuint(bcd2bin(buf[6]), == , 16);
+}
+
+uint32_t interrupt_counts[RX8900_INTERRUPT_SOURCES];
+
+/**
+ * Reset the interrupt counts
+ */
+static void count_reset(void)
+{
+ for (int source = 0; source < RX8900_INTERRUPT_SOURCES; source++) {
+ interrupt_counts[source] = 0;
+ }
+}
+
+/**
+ * Handle an RX8900 interrupt (update the counts for that interrupt type)
+ */
+static void handle_interrupt(void *opaque, const char *name, int irq,
+ bool level)
+{
+ if (!level) {
+ return;
+ }
+
+ uint8_t flags = read_register(FLAG_REGISTER);
+
+ for (int flag = 0; flag < 8; flag++) {
+ if (flags & BIT(flag)) {
+ interrupt_counts[flag]++;
+ }
+ }
+
+ write_register(FLAG_REGISTER, 0x00);
+}
+
+uint32_t fout_counts;
+
+/**
+ * Handle an Fout state change
+ */
+static void handle_fout(void *opaque, const char *name, int irq, bool level)
+{
+ if (!level) {
+ return;
+ }
+
+ fout_counts++;
+}
+
+/**
+ * Reset the fout count
+ */
+static void fout_count_reset(void)
+{
+ fout_counts = 0;
+}
+
+
+/**
+ * Sleep for some real time while counting interrupts
+ * @param delay the delay in microseconds
+ * @param loop the loop time in microseconds
+ */
+static void wait_for(uint64_t delay, uint64_t loop)
+{
+ struct timeval end, now;
+
+ gettimeofday(&end, NULL);
+ delay += end.tv_usec;
+ end.tv_sec += delay / 1000000;
+ end.tv_usec = delay % 1000000;
+
+ while (gettimeofday(&now, NULL),
+ now.tv_sec < end.tv_sec || now.tv_usec < end.tv_usec) {
+ clock_step(loop * 1000);
+ usleep(loop);
+ }
+}
+
+/**
+ * Sleep for some emulated time while counting interrupts
+ * @param delay the delay in nanoseconds
+ * @param loop the loop time in nanoseconds
+ */
+static void wait_cycles(uint64_t delay, uint64_t loop)
+{
+ uint64_t counter;
+
+ for (counter = 0; counter < delay; counter += loop) {
+ clock_step(loop);
+ }
+}
+
+
+/**
+ * Check that when the update timer interrupt is disabled, that no interrupts
+ * occur
+ */
+static void check_update_interrupt_disabled(void)
+{
+ /* Disable the update interrupt */
+ clear_bits_in_register(CONTROL_REGISTER, CTRL_MASK_UIE);
+
+ /* Wait for the clock to rollover, this will cover both seconds & minutes
+ */
+ set_time(59, 59, 23, 1, 29, 2, 16);
+
+ count_reset();
+ wait_for(2 * 1000000, 1000);
+
+ g_assert_cmpuint(interrupt_counts[FLAG_REG_UF], ==, 0);
+ g_assert_cmpuint(interrupt_counts[FLAG_REG_AF], ==, 0);
+}
+
+
+/**
+ * Check that when the update timer interrupt is enabled and configured for
+ * per second updates, that we get the appropriate number of interrupts
+ */
+static void check_update_interrupt_seconds(void)
+{
+ set_time(59, 59, 23, 1, 29, 2, 16);
+
+ /* Enable the update interrupt for per second updates */
+ clear_bits_in_register(EXTENSION_REGISTER, EXT_MASK_USEL);
+ set_bits_in_register(CONTROL_REGISTER, CTRL_MASK_UIE);
+
+ count_reset();
+ wait_for(5.1f * 1000000ULL, 1000);
+
+ /* Disable the update interrupt */
+ clear_bits_in_register(CONTROL_REGISTER, CTRL_MASK_UIE);
+
+ g_assert_cmpuint(interrupt_counts[FLAG_REG_UF], >=, 5);
+ g_assert_cmpuint(interrupt_counts[FLAG_REG_UF], <=, 6);
+ g_assert_cmpuint(interrupt_counts[FLAG_REG_AF], ==, 0);
+}
+
+/**
+ * Check that when the update timer interrupt is enabled and configured for
+ * per minute updates, that we get the appropriate number of interrupts
+ */
+static void check_update_interrupt_minutes(void)
+{
+ set_time(59, 59, 23, 1, 29, 2, 16);
+
+ /* Enable the update interrupt for per minute updates */
+ set_bits_in_register(EXTENSION_REGISTER, EXT_MASK_USEL);
+ set_bits_in_register(CONTROL_REGISTER, CTRL_MASK_UIE);
+
+ count_reset();
+ wait_for(5 * 1000000ULL, 1000);
+
+ /* Disable the update interrupt */
+ clear_bits_in_register(CONTROL_REGISTER, CTRL_MASK_UIE);
+
+ g_assert_cmpuint(interrupt_counts[FLAG_REG_UF], ==, 1);
+ g_assert_cmpuint(interrupt_counts[FLAG_REG_AF], ==, 0);
+}
+
+
+/**
+ * Check that when the alarm timer interrupt is disabled, that no interrupts
+ * occur
+ */
+static void check_alarm_interrupt_disabled(void)
+{
+ /* Disable the alarm interrupt */
+ clear_bits_in_register(CONTROL_REGISTER, CTRL_MASK_AIE);
+
+ /* Set an alarm for midnight */
+ uint8_t buf[3];
+
+ buf[0] = bin2bcd(0); /* minutes */
+ buf[1] = bin2bcd(0); /* hours */
+ buf[2] = bin2bcd(1); /* day */
+
+ write_registers(ALARM_MINUTE, buf, 3);
+
+ /* Wait for the clock to rollover */
+ set_time(59, 59, 23, 1, 29, 2, 16);
+
+ count_reset();
+ wait_for(2 * 1000000, 1000);
+
+ g_assert_cmpuint(interrupt_counts[FLAG_REG_UF], ==, 0);
+ g_assert_cmpuint(interrupt_counts[FLAG_REG_AF], ==, 0);
+}
+
+/**
+ * Check that when the alarm timer interrupt is enabled, that an interrupt
+ * occurs
+ */
+static void check_alarm_interrupt_day_of_month(void)
+{
+
+ /* Set an alarm for midnight */
+ uint8_t buf[3];
+
+ buf[0] = bin2bcd(0); /* minutes */
+ buf[1] = bin2bcd(0); /* hours */
+ buf[2] = bin2bcd(1); /* day */
+
+ write_registers(ALARM_MINUTE, buf, 3);
+
+ /* Set alarm to day of month mode */
+ set_bits_in_register(EXTENSION_REGISTER, EXT_MASK_WADA);
+
+ /* Enable the alarm interrupt */
+ set_bits_in_register(CONTROL_REGISTER, CTRL_MASK_AIE);
+
+ /* Wait for the clock to rollover */
+ set_time(59, 59, 23, 1, 29, 2, 16);
+
+ count_reset();
+ wait_for(2 * 1000000, 1000);
+
+ /* Disable the alarm interrupt */
+ clear_bits_in_register(CONTROL_REGISTER, CTRL_MASK_AIE);
+
+ g_assert_cmpuint(interrupt_counts[FLAG_REG_UF], ==, 0);
+ g_assert_cmpuint(interrupt_counts[FLAG_REG_AF], ==, 1);
+}
+
+/**
+ * Check that when the alarm timer interrupt is enabled, that an interrupt
+ * does not occur
+ */
+static void check_alarm_interrupt_day_of_month_negative(void)
+{
+
+ /* Set an alarm for midnight */
+ uint8_t buf[3];
+
+ buf[0] = bin2bcd(0); /* minutes */
+ buf[1] = bin2bcd(0); /* hours */
+ buf[2] = bin2bcd(2); /* day */
+
+ write_registers(ALARM_MINUTE, buf, 3);
+
+ /* Set alarm to day of month mode */
+ set_bits_in_register(EXTENSION_REGISTER, EXT_MASK_WADA);
+
+ /* Enable the alarm interrupt */
+ set_bits_in_register(CONTROL_REGISTER, CTRL_MASK_AIE);
+
+ /* Wait for the clock to rollover */
+ set_time(59, 59, 23, 1, 29, 2, 16);
+
+ count_reset();
+ wait_for(2 * 1000000, 1000);
+
+ /* Disable the alarm interrupt */
+ clear_bits_in_register(CONTROL_REGISTER, CTRL_MASK_AIE);
+
+ g_assert_cmpuint(interrupt_counts[FLAG_REG_UF], ==, 0);
+ g_assert_cmpuint(interrupt_counts[FLAG_REG_AF], ==, 0);
+}
+
+/**
+ * Check that when the alarm timer interrupt is enabled, that an interrupt
+ * occurs
+ */
+static void check_alarm_interrupt_day_of_week(void)
+{
+
+ /* Set an alarm for midnight */
+ uint8_t buf[3];
+
+ buf[0] = bin2bcd(0); /* minutes */
+ buf[1] = bin2bcd(0); /* hours */
+ buf[2] = 0x01 << 2; /* day */
+
+ write_registers(ALARM_MINUTE, buf, 3);
+
+ /* Set alarm to day of week mode */
+ clear_bits_in_register(EXTENSION_REGISTER, EXT_MASK_WADA);
+
+ /* Enable the alarm interrupt */
+ set_bits_in_register(CONTROL_REGISTER, CTRL_MASK_AIE);
+
+ /* Wait for the clock to rollover */
+ set_time(59, 59, 23, 1, 29, 2, 16);
+
+ count_reset();
+ wait_for(2 * 1000000, 1000);
+
+ /* Disable the alarm interrupt */
+ clear_bits_in_register(CONTROL_REGISTER, CTRL_MASK_AIE);
+
+ g_assert_cmpuint(interrupt_counts[FLAG_REG_UF], ==, 0);
+ g_assert_cmpuint(interrupt_counts[FLAG_REG_AF], ==, 1);
+}
+
+/**
+ * Check that when the alarm timer interrupt is enabled, that an interrupt
+ * does not occur
+ */
+static void check_alarm_interrupt_day_of_week_negative(void)
+{
+
+ /* Set an alarm for midnight */
+ uint8_t buf[3];
+
+ buf[0] = bin2bcd(0); /* minutes */
+ buf[1] = bin2bcd(0); /* hours */
+ buf[2] = 0x01 << 2; /* day */
+
+ write_registers(ALARM_MINUTE, buf, 3);
+
+ /* Set alarm to day of week mode */
+ clear_bits_in_register(EXTENSION_REGISTER, EXT_MASK_WADA);
+
+ /* Enable the alarm interrupt */
+ set_bits_in_register(CONTROL_REGISTER, CTRL_MASK_AIE);
+
+ /* Wait for the clock to rollover */
+ set_time(59, 59, 23, 3, 29, 2, 16);
+
+ count_reset();
+ wait_for(2 * 1000000, 1000);
+
+ /* Disable the alarm interrupt */
+ clear_bits_in_register(CONTROL_REGISTER, CTRL_MASK_AIE);
+
+ g_assert_cmpuint(interrupt_counts[FLAG_REG_UF], ==, 0);
+ g_assert_cmpuint(interrupt_counts[FLAG_REG_AF], ==, 0);
+}
+
+/**
+ * Check that the reset function
+ */
+static void check_reset(void)
+{
+ set_bits_in_register(FLAG_REGISTER, FLAG_MASK_UF);
+ set_bits_in_register(CONTROL_REGISTER, CTRL_MASK_RESET);
+
+ g_assert_cmpuint(read_register(FLAG_REGISTER), ==,
+ 0x00);
+}
+
+/**
+ * Check that Fout operates at 1Hz
+ */
+static void check_fout_1hz(void)
+{
+ uint8_t ext_reg = read_register(EXTENSION_REGISTER);
+ ext_reg |= EXT_MASK_FSEL1;
+ ext_reg &= ~EXT_MASK_FSEL0;
+ write_register(EXTENSION_REGISTER, ext_reg);
+
+ /* Enable Fout */
+ irq_set(RX8900_TEST_ID, RX8900_FOUT_ENABLE, 0, true);
+
+ fout_count_reset();
+ wait_cycles(2 * 1000000000ULL, 1000000);
+
+ /* disable Fout */
+ irq_set(RX8900_TEST_ID, RX8900_FOUT_ENABLE, 0, false);
+
+ g_assert_cmpuint(fout_counts, ==, 2);
+}
+
+/**
+ * Check that Fout operates at 1024Hz
+ */
+static void check_fout_1024hz(void)
+{
+ uint8_t ext_reg = read_register(EXTENSION_REGISTER);
+ ext_reg |= EXT_MASK_FSEL0;
+ ext_reg &= ~EXT_MASK_FSEL1;
+ write_register(EXTENSION_REGISTER, ext_reg);
+
+ /* Enable Fout */
+ irq_set(RX8900_TEST_ID, RX8900_FOUT_ENABLE, 0, true);
+
+ fout_count_reset();
+ wait_cycles(2 * 1000000000ULL, 100000);
+
+ /* disable Fout */
+ irq_set(RX8900_TEST_ID, RX8900_FOUT_ENABLE, 0, false);
+
+ g_assert_cmpuint(fout_counts, ==, 1024 * 2);
+}
+
+/**
+ * Check that Fout operates at 32768Hz
+ */
+static void check_fout_32768hz(void)
+{
+ uint8_t ext_reg = read_register(EXTENSION_REGISTER);
+ ext_reg &= ~EXT_MASK_FSEL0;
+ ext_reg &= ~EXT_MASK_FSEL1;
+ write_register(EXTENSION_REGISTER, ext_reg);
+
+ /* Enable Fout */
+ irq_set(RX8900_TEST_ID, RX8900_FOUT_ENABLE, 0, true);
+
+ fout_count_reset();
+ wait_cycles(2 * 1000000000ULL, 15000);
+
+ /* disable Fout */
+ irq_set(RX8900_TEST_ID, RX8900_FOUT_ENABLE, 0, false);
+
+ /* There appears to be some rounding errors in the timer,
+ * we'll tolerate it for now
+ */
+ g_assert_cmpuint(fout_counts, >=, 32768 * 2);
+ g_assert_cmpuint(fout_counts, <=, 65540);
+}
+
+/**
+ * Check the countdown timer operates at 1 Hz
+ */
+static void check_countdown_1hz(void)
+{
+ uint8_t ext_reg;
+
+ write_register(TIMER_COUNTER_0, 5);
+ write_register(TIMER_COUNTER_1, 0);
+
+ ext_reg = read_register(EXTENSION_REGISTER);
+ ext_reg &= ~EXT_MASK_TSEL1;
+ ext_reg |= EXT_MASK_TSEL0;
+ ext_reg |= EXT_MASK_TE;
+ write_register(EXTENSION_REGISTER, ext_reg);
+ set_bits_in_register(CONTROL_REGISTER, CTRL_MASK_TIE);
+
+ count_reset();
+ wait_cycles(5 * 1000000000ULL, 1000000);
+
+ g_assert_cmpuint(interrupt_counts[FLAG_REG_TF], ==, 0);
+
+ wait_cycles(1 * 1000000000ULL, 1000000);
+
+ g_assert_cmpuint(interrupt_counts[FLAG_REG_TF], ==, 1);
+}
+
+/**
+ * Check the countdown timer operates at 64 Hz
+ */
+static void check_countdown_64hz(void)
+{
+ uint8_t ext_reg;
+
+ write_register(TIMER_COUNTER_0, 0x40);
+ write_register(TIMER_COUNTER_1, 0x01); /* 5 * 64 */
+
+ ext_reg = read_register(EXTENSION_REGISTER);
+ ext_reg &= ~EXT_MASK_TSEL0;
+ ext_reg &= ~EXT_MASK_TSEL1;
+ ext_reg |= EXT_MASK_TE;
+ write_register(EXTENSION_REGISTER, ext_reg);
+ set_bits_in_register(CONTROL_REGISTER, CTRL_MASK_TIE);
+
+ count_reset();
+ wait_cycles(5 * 1000000000ULL, 1000000);
+
+ g_assert_cmpuint(interrupt_counts[FLAG_REG_TF], ==, 0);
+
+ wait_cycles(1 * 1000000000ULL, 1000000);
+
+ g_assert_cmpuint(interrupt_counts[FLAG_REG_TF], ==, 1);
+}
+
+/**
+ * Check the countdown timer operates at 4096 Hz
+ */
+static void check_countdown_4096hz(void)
+{
+ uint8_t ext_reg;
+
+ write_register(TIMER_COUNTER_0, 0xFF);
+ write_register(TIMER_COUNTER_1, 0x0F); /* 4095 */
+ ext_reg = read_register(EXTENSION_REGISTER);
+ ext_reg |= EXT_MASK_TSEL0;
+ ext_reg |= EXT_MASK_TSEL1;
+ ext_reg |= EXT_MASK_TE;
+ write_register(EXTENSION_REGISTER, ext_reg);
+ set_bits_in_register(CONTROL_REGISTER, CTRL_MASK_TIE);
+
+ count_reset();
+ wait_cycles(999755859ULL, 10000);
+
+ g_assert_cmpuint(interrupt_counts[FLAG_REG_TF], ==, 0);
+
+ wait_cycles(244141ULL, 10000);
+
+ g_assert_cmpuint(interrupt_counts[FLAG_REG_TF], ==, 1);
+}
+
+/**
+ * Check the countdown timer operates at 1 minute
+ */
+static void check_countdown_1m(void)
+{
+ uint8_t ext_reg;
+
+ write_register(TIMER_COUNTER_0, 0x01);
+ write_register(TIMER_COUNTER_1, 0x00);
+ ext_reg = read_register(EXTENSION_REGISTER);
+ ext_reg &= ~EXT_MASK_TSEL0;
+ ext_reg |= EXT_MASK_TSEL1;
+ ext_reg |= EXT_MASK_TE;
+ write_register(EXTENSION_REGISTER, ext_reg);
+ set_bits_in_register(CONTROL_REGISTER, CTRL_MASK_TIE);
+
+ count_reset();
+ wait_cycles(59 * 1000000000ULL, 100000);
+
+ g_assert_cmpuint(interrupt_counts[FLAG_REG_TF], ==, 0);
+
+ wait_cycles(1000000001LL, 100000);
+
+ g_assert_cmpuint(interrupt_counts[FLAG_REG_TF], ==, 1);
+}
+
+/**
+ * Check that the voltage can be altered via properties
+ */
+static void check_voltage(void)
+{
+ uint8_t flags = read_register(FLAG_REGISTER) &
+ (FLAG_MASK_VDET | FLAG_MASK_VLF);
+
+ /* start from a good state */
+ g_assert_cmpuint(flags, == , 0x00);
+
+ /* 1.9V triggers VDET but not VLF */
+ qmp_rx8900_set_voltage(RX8900_TEST_ID, 1.9f);
+
+ flags = read_register(FLAG_REGISTER) & (FLAG_MASK_VDET | FLAG_MASK_VLF);
+ g_assert_cmpuint(flags, == , FLAG_MASK_VDET);
+
+ /* Clearing the flag should reassert it as the voltage is still low */
+ write_register(FLAG_REGISTER, 0x00);
+
+ flags = read_register(FLAG_REGISTER) & (FLAG_MASK_VDET | FLAG_MASK_VLF);
+ g_assert_cmpuint(flags, == , FLAG_MASK_VDET);
+
+ /* Set the voltage to a good level, the low voltage flag should persist */
+ qmp_rx8900_set_voltage(RX8900_TEST_ID, 3.3f);
+
+ flags = read_register(FLAG_REGISTER) & (FLAG_MASK_VDET | FLAG_MASK_VLF);
+ g_assert_cmpuint(flags, == , FLAG_MASK_VDET);
+
+ /* We should be able to clear the flag with a good voltage */
+ write_register(FLAG_REGISTER, 0x00);
+
+ flags = read_register(FLAG_REGISTER) & (FLAG_MASK_VDET | FLAG_MASK_VLF);
+ g_assert_cmpuint(flags, == , 0x00);
+
+
+ /* 1.5V should trigger both VDET & VLF */
+ qmp_rx8900_set_voltage(RX8900_TEST_ID, 1.5f);
+ flags = read_register(FLAG_REGISTER) & (FLAG_MASK_VDET | FLAG_MASK_VLF);
+ g_assert_cmpuint(flags, == , FLAG_MASK_VDET | FLAG_MASK_VLF);
+
+
+ /* Clearing the flag should reassert it as the voltage is still low */
+ write_register(FLAG_REGISTER, 0x00);
+
+ flags = read_register(FLAG_REGISTER) & (FLAG_MASK_VDET | FLAG_MASK_VLF);
+ g_assert_cmpuint(flags, == , FLAG_MASK_VDET | FLAG_MASK_VLF);
+
+ /* Set the voltage to a good level, the low voltage flag should persist */
+ qmp_rx8900_set_voltage(RX8900_TEST_ID, 3.3f);
+
+ flags = read_register(FLAG_REGISTER) & (FLAG_MASK_VDET | FLAG_MASK_VLF);
+ g_assert_cmpuint(flags, == , FLAG_MASK_VDET | FLAG_MASK_VLF);
+
+ /* We should be able to clear the flag with a good voltage */
+ write_register(FLAG_REGISTER, 0x00);
+
+ flags = read_register(FLAG_REGISTER) & (FLAG_MASK_VDET | FLAG_MASK_VLF);
+ g_assert_cmpuint(flags, == , 0);
+}
+
+
+
+int main(int argc, char **argv)
+{
+ QTestState *s = NULL;
+ int ret;
+ char args[255];
+ snprintf(args, sizeof(args), "-display none -machine imx25-pdk "
+ "-device rx8900,bus=i2c-bus.0,address=0x%x,id=%s"
+#ifdef RX8900_TRACE
+ " -trace events=/tmp/events"
+#endif
+ ,
+ RX8900_ADDR, RX8900_TEST_ID);
+
+ g_test_init(&argc, &argv, NULL);
+
+ s = qtest_start(args);
+ i2c = imx_i2c_create(IMX25_I2C_0_BASE);
+ addr = RX8900_ADDR;
+
+ irq_intercept_out(RX8900_TEST_ID);
+ irq_attach(RX8900_INTERRUPT_OUT, 0, handle_interrupt, NULL);
+ irq_attach(RX8900_FOUT, 0, handle_fout, NULL);
+
+ qtest_add_func("/rx8900/reset", check_reset);
+ qtest_add_func("/rx8900/tx-rx", send_and_receive);
+ qtest_add_func("/rx8900/temperature", check_temperature);
+ qtest_add_func("/rx8900/rollover", check_rollover);
+ qtest_add_func("/rx8900/update-interrupt-disabled",
+ check_update_interrupt_disabled);
+ qtest_add_func("/rx8900/update-interrupt-seconds",
+ check_update_interrupt_seconds);
+ qtest_add_func("/rx8900/update-interrupt-minutes",
+ check_update_interrupt_minutes);
+ qtest_add_func("/rx8900/alarm-interrupt-disabled",
+ check_alarm_interrupt_disabled);
+ qtest_add_func("/rx8900/alarm-interrupt-month",
+ check_alarm_interrupt_day_of_month);
+ qtest_add_func("/rx8900/alarm-interrupt-month-negative",
+ check_alarm_interrupt_day_of_month_negative);
+ qtest_add_func("/rx8900/alarm-interrupt-week",
+ check_alarm_interrupt_day_of_week);
+ qtest_add_func("/rx8900/alarm-interrupt-week-negative",
+ check_alarm_interrupt_day_of_week_negative);
+ qtest_add_func("/rx8900/fout_1hz", check_fout_1hz);
+ qtest_add_func("/rx8900/fout_1024hz", check_fout_1024hz);
+ qtest_add_func("/rx8900/fout_32768hz", check_fout_32768hz);
+ qtest_add_func("/rx8900/countdown_1hz", check_countdown_1hz);
+ qtest_add_func("/rx8900/countdown_64hz", check_countdown_64hz);
+ qtest_add_func("/rx8900/countdown_4096hz", check_countdown_4096hz);
+ qtest_add_func("/rx8900/countdown_1m", check_countdown_1m);
+ qtest_add_func("/rx8900/low_voltage", check_voltage);
+
+ ret = g_test_run();
+
+ if (s) {
+ qtest_quit(s);
+ }
+ g_free(i2c);
+
+ return ret;
+}
--
2.9.3
^ permalink raw reply related [flat|nested] 16+ messages in thread* [Qemu-arm] [PATCH v3 7/7] arm: Add an RX8900 RTC to the ASpeed board
2016-12-02 5:46 [Qemu-arm] [PATCH v3 0/7] Add support for the Epson RX8900 RTC to the aspeed board Alastair D'Silva
` (5 preceding siblings ...)
2016-12-02 5:46 ` [Qemu-arm] [PATCH v3 6/7] tests: Test all implemented RX8900 functionality Alastair D'Silva
@ 2016-12-02 5:46 ` Alastair D'Silva
6 siblings, 0 replies; 16+ messages in thread
From: Alastair D'Silva @ 2016-12-02 5:46 UTC (permalink / raw)
To: qemu-arm
Cc: Peter Maydell, Andrew Jeffery, qemu-devel, Chris Smart,
Joel Stanley, Alastair D'Silva, Cédric Le Goater
From: Alastair D'Silva <alastair@d-silva.org>
Connect an RX8900 RTC to i2c12 of the AST2500 SOC at address 0x32
Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
Signed-off-by: Chris Smart <chris@distroguy.com>
---
hw/arm/aspeed.c | 58 +++++++++++++++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 56 insertions(+), 2 deletions(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index c7206fd..7445242 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -26,6 +26,20 @@ static struct arm_boot_info aspeed_board_binfo = {
.nb_cpus = 1,
};
+typedef struct IRQConfig {
+ const char *name;
+ int irq;
+ int nvic_irq;
+} IRQConfig;
+
+typedef struct AspeedI2CDevice {
+ const char *type;
+ uint8_t address;
+ int bus;
+ /* device_inputs not yet implemented */
+ const IRQConfig *device_outputs;
+} AspeedI2CDevice;
+
typedef struct AspeedBoardState {
AspeedSoCState soc;
MemoryRegion ram;
@@ -34,6 +48,7 @@ typedef struct AspeedBoardState {
typedef struct AspeedBoardConfig {
const char *soc_name;
uint32_t hw_strap1;
+ const AspeedI2CDevice *i2c_devices;
} AspeedBoardConfig;
enum {
@@ -64,9 +79,25 @@ enum {
SCU_HW_STRAP_MAC0_RGMII) & \
~SCU_HW_STRAP_2ND_BOOT_WDT)
+static const IRQConfig rx8900_out[] = {
+ {"rx8900-interrupt-out", 0, 22},
+ {NULL}
+};
+
+static const AspeedI2CDevice ast2500_i2c_devices[] = {
+ {"rx8900", 0x32, 11, rx8900_out},
+ {NULL}
+};
+
static const AspeedBoardConfig aspeed_boards[] = {
- [PALMETTO_BMC] = { "ast2400-a0", PALMETTO_BMC_HW_STRAP1 },
- [AST2500_EVB] = { "ast2500-a1", AST2500_EVB_HW_STRAP1 },
+ [PALMETTO_BMC] = {
+ "ast2400-a0", PALMETTO_BMC_HW_STRAP1,
+ NULL
+ },
+ [AST2500_EVB] = {
+ "ast2500-a1", AST2500_EVB_HW_STRAP1,
+ ast2500_i2c_devices
+ },
};
static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
@@ -95,6 +126,27 @@ static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
}
}
+static void aspeed_i2c_init(AspeedBoardState *bmc,
+ const AspeedBoardConfig *cfg)
+{
+ AspeedSoCState *soc = &bmc->soc;
+ const AspeedI2CDevice *dev;
+ const IRQConfig *out;
+
+ for (dev = cfg->i2c_devices; dev != NULL && dev->type != NULL; dev++) {
+ I2CBus *i2c_bus = aspeed_i2c_get_bus((DeviceState *)&soc->i2c,
+ dev->bus);
+ DeviceState *i2c_slave = i2c_create_slave(i2c_bus, dev->type,
+ dev->address);
+
+ for (out = dev->device_outputs; out != NULL && out->name != NULL;
+ out++) {
+ qdev_connect_gpio_out_named(i2c_slave, out->name, out->irq,
+ qdev_get_gpio_in(DEVICE(&soc->vic), out->nvic_irq));
+ }
+ }
+}
+
static void aspeed_board_init(MachineState *machine,
const AspeedBoardConfig *cfg)
{
@@ -137,6 +189,8 @@ static void aspeed_board_init(MachineState *machine,
aspeed_board_binfo.ram_size = ram_size;
aspeed_board_binfo.loader_start = sc->info->sdram_base;
+ aspeed_i2c_init(bmc, cfg);
+
arm_load_kernel(ARM_CPU(first_cpu), &aspeed_board_binfo);
}
--
2.9.3
^ permalink raw reply related [flat|nested] 16+ messages in thread