From: "Alastair D'Silva" <alastair@au1.ibm.com>
To: qemu-arm <qemu-arm@nongnu.org>, QEMU Developers <qemu-devel@nongnu.org>
Cc: "Andrew Jeffery" <andrew@aj.id.au>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Alastair D'Silva" <alastair@d-silva.org>,
"Cédric Le Goater" <clg@kaod.org>,
"Joel Stanley" <joel@jms.id.au>
Subject: [Qemu-arm] [PATCH v5 3/7] qtest: Support setting named GPIOs
Date: Thu, 5 Jan 2017 15:34:26 +1100 [thread overview]
Message-ID: <20170105043430.3176-4-alastair@au1.ibm.com> (raw)
In-Reply-To: <20170105043430.3176-1-alastair@au1.ibm.com>
From: Alastair D'Silva <alastair@d-silva.org>
Some devices change their behaviour based on the state of their input GPIO
lines.
This patch allows testing of the variable behaviour by providing facilities
for the test to set the state of these GPIO lines.
Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
---
qtest.c | 42 ++++++++++++++++++++++++++++++++++++++++++
tests/libqtest.c | 7 +++++++
tests/libqtest.h | 29 +++++++++++++++++++++++++++++
3 files changed, 78 insertions(+)
diff --git a/qtest.c b/qtest.c
index ad7e215..a947892 100644
--- a/qtest.c
+++ b/qtest.c
@@ -165,6 +165,11 @@ static bool qtest_opened;
* where NUM is an IRQ number. For the PC, interrupts can be intercepted
* simply with "irq_intercept_in ioapic" (note that IRQ0 comes out with
* NUM=0 even though it is remapped to GSI 2).
+ *
+ * > irq_set NAME NUM LEVEL
+ * < OK
+ *
+ * Set the named input IRQ to the level (0/1)
*/
static int hex2nib(char ch)
@@ -344,6 +349,43 @@ static void qtest_process_command(CharBackend *chr, gchar **words)
qtest_send_prefix(chr);
qtest_send(chr, "OK\n");
+ } else if (strcmp(words[0], "irq_set") == 0) {
+ DeviceState *dev;
+ NamedGPIOList *ngl;
+ int level;
+ qemu_irq irq = NULL;
+ int irq_num;
+
+ g_assert(words[1]); /* device */
+ g_assert(words[2]); /* gpio list */
+ g_assert(words[3]); /* gpio line in list */
+ g_assert(words[4]); /* level */
+ dev = DEVICE(object_resolve_path(words[1], NULL));
+ if (!dev) {
+ qtest_send_prefix(chr);
+ qtest_send(chr, "FAIL Unknown device\n");
+ return;
+ }
+
+ irq_num = atoi(words[3]);
+ level = atoi(words[4]);
+
+ QLIST_FOREACH(ngl, &dev->gpios, node) {
+ if (strcmp(words[2], ngl->name) == 0 && ngl->num_in > irq_num) {
+ irq = ngl->in[irq_num];
+ }
+ }
+
+ if (irq == NULL) {
+ qtest_send_prefix(chr);
+ qtest_send(chr, "FAIL Unknown IRQ\n");
+ return;
+ }
+
+ qemu_set_irq(irq, level);
+
+ qtest_send_prefix(chr);
+ qtest_send(chr, "OK\n");
} else if (strcmp(words[0], "outb") == 0 ||
strcmp(words[0], "outw") == 0 ||
strcmp(words[0], "outl") == 0) {
diff --git a/tests/libqtest.c b/tests/libqtest.c
index a433c3b..a7cdd3b 100644
--- a/tests/libqtest.c
+++ b/tests/libqtest.c
@@ -988,3 +988,10 @@ bool qtest_big_endian(QTestState *s)
{
return s->big_endian;
}
+
+void qtest_irq_set(QTestState *s, const char *id, const char *gpiolist, int n,
+ bool level)
+{
+ qtest_sendf(s, "irq_set %s %s %d %d\n", id, gpiolist, n, level);
+ qtest_rsp(s, 0);
+}
diff --git a/tests/libqtest.h b/tests/libqtest.h
index 99b14b1..3063bc9 100644
--- a/tests/libqtest.h
+++ b/tests/libqtest.h
@@ -190,6 +190,20 @@ void qtest_irq_attach(QTestState *s, const char *name, int irq,
void *opaque);
/**
+ * qtest_irq_set:
+ * Set an interrupt level
+ * @s: #QTestState instance to operate on.
+ * @id: the device to inject interrupts for
+ * @gpiolist: the GPIO list containing the IRQ
+ * @n: the GPIO within the list
+ * @level: the IRQ level
+ *
+ * Set an interrupt to a nominated level
+ */
+void qtest_irq_set(QTestState *s, const char *id, const char *gpiolist, int n,
+ bool level);
+
+/**
* qtest_outb:
* @s: #QTestState instance to operate on.
* @addr: I/O port to write to.
@@ -656,6 +670,21 @@ static inline void irq_attach(const char *name, int irq,
}
/**
+ * qtest_irq_set
+ * Set an interrupt level
+ * @id: the device to inject interrupts for
+ * @gpiolist: the GPIO list containing the line to seh
+ * @n: the line to set within the list
+ * @level: the IRQ level
+ */
+static inline void irq_set(const char *id, const char *gpiolist, int n,
+ bool level)
+{
+ qtest_irq_set(global_qtest, id, gpiolist, n, level);
+}
+
+
+/**
* outb:
* @addr: I/O port to write to.
* @value: Value being written.
--
2.9.3
next prev parent reply other threads:[~2017-01-05 4:40 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-05 4:34 [Qemu-devel] [PATCH v5 0/7] Add support for the Epson RX8900 RTC to the aspeed board Alastair D'Silva
2017-01-05 4:34 ` [Qemu-devel] [PATCH v5 1/7] arm: Uniquely name imx25 I2C buses Alastair D'Silva
2017-01-16 14:58 ` [Qemu-arm] " Peter Maydell
2017-01-05 4:34 ` [Qemu-devel] [PATCH v5 2/7] qtest: Support named interrupts Alastair D'Silva
2017-01-16 14:58 ` Peter Maydell
2017-01-05 4:34 ` Alastair D'Silva [this message]
2017-01-16 15:00 ` [Qemu-arm] [PATCH v5 3/7] qtest: Support setting named GPIOs Peter Maydell
2017-01-05 4:34 ` [Qemu-devel] [PATCH v5 4/7] qtest: Fix whitespace Alastair D'Silva
2017-01-16 15:00 ` Peter Maydell
2017-01-05 4:34 ` [Qemu-devel] [PATCH v5 5/7] hw/timer: Add Epson RX8900 RTC support Alastair D'Silva
2017-01-16 15:53 ` [Qemu-arm] " Peter Maydell
2017-01-05 4:34 ` [Qemu-arm] [PATCH v5 6/7] tests: Test all implemented RX8900 functionality Alastair D'Silva
2017-01-05 4:34 ` [Qemu-devel] [PATCH v5 7/7] arm: Add an RX8900 RTC to the ASpeed board Alastair D'Silva
2017-01-05 4:46 ` [Qemu-devel] [PATCH v5 0/7] Add support for the Epson RX8900 RTC to the aspeed board no-reply
2017-01-05 4:53 ` [Qemu-arm] " no-reply
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